MINIMUM-SIZE BELIEF PROPAGATION NETWORK FOR FEC ITERATIVE ENCODERS AND DECODERS AND RELATED ROUTING METHOD

摘要

The invention relates to an interconnection network (110, 200) for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. N is a non-prime positive integer, and M is a positive integer equal to, or higher than, two. The M stages include a first stage and a last stage. Each stage includes switching elements (111, 112, 113) having, each, respective input pins and respective output pins. The input pins of the switching elements (112) of the first stage are connected to the input terminals, and the output pins of the switching elements (113) of the last stage are connected to the output terminals. The input and output pins of the switching elements (111, 112, 113) of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing, each, respective input values from respective output pins of the switching elements (112) of the first stage to respective input pins of the switching elements (113) of the last stage. The interconnection network (110, 200) is operable to route, on the basis of routing commands applied to the switching elements (111, 112, 113), N input values received at the N input terminals through the M stages and the interconnection sub-networks to provide, at the N output terminals, N output values corresponding to, or circularly shifted with respect to, said N input values received at the N input terminals. Additionally, M denotes a number of given submultiples of N whose product is equal to N. Each stage is associated with a respective submultiple of said M given submultiples of N, and includes S_i switching elements (111, 112, 113), each having sm_i respective input pins and sm_i respective output pins, wherein S_i = N/sm_i, wherein sm_i denotes said respective submultiple associated with said stage, and wherein i denotes said stage and is a positive integer comprised between one and M. Each switching element (111, 112, 113) is configured to: receive, at the sm_i respective input pins, sm_i respective input values; and provide at the sm_i respective output pins, on the basis of a respective routing command applied to said switching element (111, 112, 113), sm_i respective output values corresponding to, or circularly shifted with respect to, said sm_i respective input values received at the sm_i respective input pins. The interconnection sub-networks are not connected to each other. The interconnection network includes sm₁ interconnection sub-networks for routing, each, N/sm₁ respective input values from N/sm₁ respective output pins of the switching elements (112) of the first stage to N/sm₁ respective input pins of the switching elements (113) of the last stage; wherein sm₁ denotes the submultiple, among said M given submultiples of N, which is associated with the first stage.