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3D PIXEL CIRCUIT FOR MICRODISPLAY WITH REDUCED PIXEL SIZE AND METHOD OF FORMING SAME
3D PIXEL CIRCUIT FOR MICRODISPLAY WITH REDUCED PIXEL SIZE AND METHOD OF FORMING SAME
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机译:具有减小的像素尺寸的微显示器的3D像素电路及其形成方法
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摘要
A vertically stacked pixel circuit is provided that includes a high voltage device for driving a pixel on an upper silicon layer, and low voltage circuitry (such as matrix addressing circuitry, data storage circuitry and uniformity compensation circuitry) on a lower silicon layer. The circuitry on the upper and lower silicon layers are electrically connected via a through-silicon via. This unique arrangement allows the high voltage device for driving a pixel to be physically located on top of the larger number of low voltage devices in the lower silicon layer in order to achieve a substantial reduction in overall pixel emission area. The vertically stacked pixel circuit is particularly suited for organic light-emitting diode microdisplays.
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