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3D pixel circuit for microdisplay with reduced pixel size and method for forming same

机译:用于具有减小的像素尺寸的微型显示器的3D像素电路及其形成方法

摘要

A vertical stack type comprising a high voltage device for driving a pixel on the upper silicon layer, and a low voltage circuit on the lower silicon layer (e.g., matrix addressing circuit, data storage circuit and uniformity compensation circuit) A vertically stacked) pixel circuit is provided. Circuits on the upper silicon layer and the lower silicon layer are electrically connected through a through-silicon electrode. This unique arrangement allows the high voltage device for driving a pixel to be physically located on top of a larger number of low voltage devices in the lower silicon layer, so that a substantial reduction of the entire pixel emission area can be achieved. The vertically stacked pixel circuit is particularly suitable for an organic light emitting diode microdisplay.
机译:垂直堆叠型,包括用于驱动上硅层上的像素的高压装置和下硅层上的低压电路(例如,矩阵寻址电路,数据存储电路和均匀性补偿电路)。提供。上硅层和下硅层上的电路通过硅穿透电极电连接。这种独特的布置使得用于驱动像素的高压器件物理上位于下部硅层中的大量低压器件的顶部,从而可以实现整个像素发射面积的显着减小。垂直堆叠的像素电路特别适用于有机发光二极管微型显示器。

著录项

  • 公开/公告号KR20200123204A

    专利类型

  • 公开/公告日2020-10-28

    原文格式PDF

  • 申请/专利权人 이매진 코퍼레이션;

    申请/专利号KR20207027113

  • 发明设计人 와시크 이호르;

    申请日2019-02-20

  • 分类号H01L27/32;G09G3/3208;H01L21/822;H01L27/06;H01L27/088;

  • 国家 KR

  • 入库时间 2022-08-21 11:05:42

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