首页> 外国专利> SEMICONDUCTOR ASSEMBLIES HAVING SEMICONDUCTOR MATERIAL REGIONS WITH CONTOURED UPPER SURFACES; AND METHODS OF FORMING SEMICONDUCTOR ASSEMBLIES UTILIZING ETCHING TO CONTOUR UPPER SURFACES OF SEMICONDUCTOR MATERIAL

SEMICONDUCTOR ASSEMBLIES HAVING SEMICONDUCTOR MATERIAL REGIONS WITH CONTOURED UPPER SURFACES; AND METHODS OF FORMING SEMICONDUCTOR ASSEMBLIES UTILIZING ETCHING TO CONTOUR UPPER SURFACES OF SEMICONDUCTOR MATERIAL

机译:具有半导电上表面的半导电材料区域的半导电组件;利用刻蚀在半导体材料的上表面上修整形成半导体组件的方法和方法

摘要

Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat- topped peak portion and an adjacent concavity portion.
机译:一些实施例包括具有第一半导体材料的区域的集成组件。该区域沿横截面具有上表面。上表面具有平顶峰和与平顶峰相邻的凹面。第二半导体材料的柱在该区域上方并且直接抵靠该区域。支柱从上表面垂直延伸。一些实施例包括形成集成组件的方法。形成具有半导体区域以及具有在半导体区域上方并与半导体区域并排延伸的绝缘区域的构造。利用三种刻蚀的组合来暴露半导体区域的上表面并修改半导体区域的上表面以形成所述上表面,以沿横截面包括平顶的峰部和相邻的凹面。一部分。

著录项

  • 公开/公告号WO2019172970A1

    专利类型

  • 公开/公告日2019-09-12

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号WO2018US60892

  • 发明设计人 SHARMA PRANAV P.;NAIR VINAY;SAPRA SANJEEV;

    申请日2018-11-14

  • 分类号H01L27/108;

  • 国家 WO

  • 入库时间 2022-08-21 11:53:18

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