3D DYNAMIC ERASE VOLTAGE STEP SIZE SELECTION FOR 3D NON-VOLATILE MEMORY

摘要

Techniques are provided for erasing memory cells in a 3D stacked non-volatile memory device in a manner that prevents the erase time from increasing when the erase speed is reduced due to the accumulation of program-erase cycles. In particular, the step size of the erase pulses may be determined by, for example, a set of functions of the number of program-erase cycles indicated by a count of program-erase cycles, a loop count during programming, Lt; / RTI may be an initial program voltage that is a function. The erase operation may also count different erase rates of memory cells in different word line layers.