FPGA Method and Apparatus for FPGA Bitstream Reverse-Engineering Based on Machine Learning

摘要

The present invention relates to a method and apparatus for field programmable gate array (FPGA) bitstream reverse engineering. The method for FPGA bitstream reverse engineering based on machine learning according to the present invention comprises the steps of: selecting a logic primitive and constraint representing logic of a bitstream and generating the bitstream using a predetermined utility; extracting and compressing configuration data defined as bitstream data for the logic; and inputting a dataset, which is a result of extracting and compressing the configuration data, into a predetermined machine learning model and performing machine learning and reverse engineering.