FPGA Method and Apparatus for FPGA Bitstream Reverse-Engineering Based on Machine Learning

摘要

The present invention relates to a field programmable gate array (FPGA) bitstream reverse engineering method and apparatus. In the machine learning-based FPGA bitstream reverse engineering method according to the present invention, a logic primitive and a constraint that can express the logic of the bitstream are selected, and the bitstream is obtained using a predetermined utility. Generating a; Extracting and compressing configuration data defined as bitstream data for the logic; And inputting a data set resulting from the extraction and compression of the configuration data into a predetermined machine learning model to perform machine learning and reverse engineering.