-- FABRIC INTERCONNECTION FOR MEMORY BANKS BASED ON NETWORK-ON-CHIP METHODOLOGY

摘要

The implementations disclosed herein generally relate to the use of a network-on-a-chip architecture for volatile and non-volatile solid state memory structures that provide access to memory storage blocks through a router. As such, data may be transferred from / to the memory storage blocks as data packets on the chip. The network-on-chip architecture can be further used to interconnect unlimited memory cell matrices applied on a die, thereby reducing the latency between the matrices, selective power control, infinite memory density growth without major latency penalties , And reduced parasitic capacitance and resistance. Other advantages may include improved signal integrity, larger die area available for implementation of memory arrays, and higher operating frequency.