Evaluation of compact multi-bank memory using multi-stage interconnection network

摘要

It is common to use crossbar network which is based on non-blocking network architecture for combination between the processors and a memory in the conventional multi-banks memory system. But, these conventional memory system can not achive high memory access bandwidth within small chip area. Therefore, adopting blocking network is proposed. However, compared with non-blocking network, the rate of access passage declines in blocking network. EBSF (Expanded Banyan Switching Fabrics) is proposed as a solution to this problem. This paper proposes to add aome stages to EBSF and applies this blocking network with multi-bank memory system, evaluates the proposal method by using a benchmark program. According to the evaluation results, the proposal method succeeded in holding 10% or less increase of processing time, and reducing a circuit scale to 1/10 by compared with conventional method.