首页> 外国专利> SEMICONDUCTOR ARRANGEMENT, METHOD FOR PRODUCING A NUMBER OF CHIP ASSEMBLIES, METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT, AND METHOD FOR OPERATING A SEMICONDUCTOR ARRANGEMENT

SEMICONDUCTOR ARRANGEMENT, METHOD FOR PRODUCING A NUMBER OF CHIP ASSEMBLIES, METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT, AND METHOD FOR OPERATING A SEMICONDUCTOR ARRANGEMENT

机译:半导体布置,用于制造多个芯片组件的方法,用于制造半导体布置的方法以及用于操作半导体布置的方法

摘要

Semiconductor device comprising: an upper contact plate (41) and a lower contact plate (42); a number of chip assemblies (2), each having: - A semiconductor chip (1) having a semiconductor body (10), wherein the semiconductor body (10) has an upper side and an upper side opposite the upper side, and wherein the upper side in a vertical direction (v) is spaced from the underside; - An upper main electrode arranged on the top (11); - A arranged on the bottom lower main electrode (12); - a control electrode (13) arranged at the top, by means of which an electric current can be controlled between the upper main electrode (11) and the lower main electrode (12); and - An electrically conductive upper compensating plate (21) disposed on the semiconductor body (10) facing away from the upper main electrode (11) and by means of an upper connecting layer (31) to the upper main electrode (11) is integrally connected and electrically conductive; a dielectric investment material (4), by means of which the chip assemblies (2) are materially connected to one another in a solid composite (6), the side of the upper compensation chip (21) facing away from the semiconductor body (10) in each of the chip assemblies (2) relevant chip assembly (2) are not or at least not completely covered by the investment material (4); a control electrode interconnection structure (70) disposed on the fixed structure (6) and electrically connecting the control electrodes (13) of the chip assemblies (2) with each other; in which each of the chip assemblies (2) being arranged between the upper contact plate (41) and the lower contact plate (42) such that in this chip assembly (2) the side of the upper compensation chip (21) facing away from the semiconductor body (10) is the upper contact plate (12). 41) contacted electrically.
机译:半导体装置,包括:上接触板(41)和下接触板(42);多个芯片组件(2),每个具有:-具有半导体本体(10)的半导体芯片(1),其中该半导体本体(10)具有上侧和与上侧相对的上侧,并且其中垂直方向(v)的上侧与下侧隔开; -上部主电极布置在顶部(11); -在下部下部主电极(12)上布置一个A; -布置在顶部的控制电极(13),通过该控制电极可以控制上部主电极(11)和下部主电极(12)之间的电流; -导电的上补偿板(21),其设置在背离上主电极(11)并通过上连接层(31)连接到上主电极(11)的半导体本体(10)上连接且导电;一种介电投资材料(4),通过这些材料,芯片组件(2)在固态复合材料(6)中彼此牢固连接,上补偿芯片(21)的一侧背离半导体本体(10) )在每个芯片组件(2)中,相关芯片组件(2)没有或至少没有完全被投资材料(4)覆盖;控制电极互连结构(70),其布置在固定结构(6)上,并使芯片组件(2)的控制电极(13)彼此电连接;其中每个芯片组件(2)布置在上接触板(41)和下接触板(42)之间,使得在该芯片组件(2)中,上补偿芯片(21)的背对侧面半导体本体(10)是上接触板(12)。 41)电气接触。

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