Formation of a symmetric extension junction with a low K spacer and dual epitaxial process in a FinFET device

摘要

A method (300) for a dual epitaxial process in a FinFET device (200), the method (300) comprising: Arranging (305) a first spacer layer (18) on a substrate (10), on a dummy gate (14) and on a hard mask (16), wherein a first area protrudes from a location on the dummy gate (14) extending in a first direction and a second area extending from the location on the dummy gate (14) in a second direction, the first direction being opposite to the second direction; Arranging (310) an intermediate spacer layer (205) on top of the first spacer layer (18), the intermediate spacer layer (205) including a dopant (28); Opening (315) a first region (250) on the substrate (10) by removing the first spacer layer (18) and the intermediate spacer layer (205) at the first region (250); Arranging (320) a first epitaxial layer in the first region (250) on the substrate (10); Removing (325) the intermediate spacer layer (205) from the first region; Arranging (330) a second spacer layer (38) on the intermediate spacer layer (205); Opening (335) a second region (260) on the substrate (10) by exposing the first spacer layer (18), the intermediate spacer layer (205), and the second spacer layer (38) to the second region (260) on the substrate (10 ) are removed; Placing (340) a second epitaxial layer in the second region (260) on the substrate (10), the first region (250) and the second region (260) being on opposite sides of the dummy gate (14); and Increasing (345) a width of the second epitaxial layer by annealing to cause the dopant (28) in the intermediate spacer layer (205) to flow into the second epitaxial layer.