Apparatus and method for complex multiplication and accumulation

摘要

One embodiment of the invention is a processor having execution circuitry for computing a result of a complex multiplication accumulation of a first complex number, a second complex number, and a third complex number in response to a decoded instruction. The computation includes a first operation to compute a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder for decoding an instruction to generate the decoded instruction, and a first source register, a second source register, and a source and destination register for the first complex number, the second complex number, and the third complex, respectively Number to provide.