System and method for increasing the resolution of on-chip timing uncertainty measurements

摘要

A system for increasing the resolution of on-chip timing uncertainty measurements. A system includes a set of delay circuits logically coupled in a chain configuration and a plurality of flip-flop circuits each logically coupled to a delay output of each delay circuit of the delay circuits. A plurality of flip-flop circuits forming a stage of the flip-flop circuit, and a clock circuit logically coupled to each of the stages of the flip-flop circuit. The circuit is responsive to a delay input of a first delay circuit in the set of delay circuits receiving an output from the programmable delay circuit and a skewed clock signal from the clock circuit. Then, the edge signals transmitted from the delay outputs of the respective delay circuits of the delay circuits are logically configured to indicate how far the edge signals have propagated in the plurality of flip-flop circuits. [Selection diagram] Fig. 3