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Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation

机译:用于处理与条件存储操作有关的已缓存数据的所有权升级请求的处理装置和方法

摘要

An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units. The coherent interconnect may receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data. The coherent interconnect is arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed. In that event, a pass condition is identified for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.
机译:提供了一种用于处理与缓存的数据有关的所有权升级请求的装置和方法。该设备具有多个处理单元,其中至少一些具有关联的高速缓存存储。一致性互连将多个主控单元与存储器耦合,该一致性互连具有探听单元,该探听单元用于在一致性互连接收到的请求标识存储器内的可缓存存储器地址时实现高速缓存一致性协议。提供竞争管理电路以控制多个处理单元中的两个或多个处理单元对存储器地址的竞争访问。相干互连可以从具有相关联的高速缓存存储器的第一处理单元接收指定目标存储器地址的所有权升级请求,该所有权升级请求指示在目标存储器地址处的数据的副本,如保持在共享状态中。在发出所有权升级请求时,要求第一处理单元的关联缓存存储在第一处理电路对数据执行写操作之前使其状态从共享状态更改为唯一状态。一致性互连被安排为通过引用侦听单元来处理所有权升级请求,以便确定在所有权升级请求时,是否将第一处理单元的关联缓存存储标识为仍在目标存储地址保存数据的副本。已处理。在那种情况下,针对所有权升级请求确定通过条件,而与争用管理电路为目标存储器地址持有的信息无关。

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