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Efficient signaling scheme for high-speed ultra short reach interfaces
Efficient signaling scheme for high-speed ultra short reach interfaces
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机译:高速超短距离接口的高效信令方案
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摘要
A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.
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