Memory interface and memory system including plurality of delay adjustment circuits shared by memory read and write circuits for adjusting the timing of read and write data signals

摘要

A memory interface includes a first output circuit to be connected to the memory device for communication therewith, a first input circuit to be connected to the memory device for communication therewith, a first write circuit configured to process write data, a read circuit configured to process read data and a read strobe, a first delay adjustment circuit, a first switching circuit which is connected in a signal path between the first write circuit and the first delay adjustment circuit, and in a signal path between the first input circuit and the first delay adjustment circuit, and a second switching circuit which is connected in a signal path between the first delay adjustment circuit and the first output circuit, and in a signal path between the first delay adjustment circuit and the read circuit.