Methods, circuits, systems, and articles of manufacture for state machine interconnect architecture using embedded DRAM

摘要

A finite state machine circuit can include a plurality of rows of gain cell embedded Dynamic Random Access Memory (GC-eDRAM) cells that can be configured to store state information representing all N states expressed by a finite state machine circuit. A number of eDRAM switch cells can be electrically coupled to the plurality of rows of the GC-eDRAM cells, where the number of eDRAM switch cells can be arranged in an M×M cross-bar array where M is less than N, and the number of eDRAM switch cells can be configured to provide interconnect for all transitions between the all N states expressed by the finite state machine circuit.