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25 DUTY CYCLE CLOCK GENERATOR HAVING A DIVIDER WITH AN INVERTER RING ARRANGEMENT
25 DUTY CYCLE CLOCK GENERATOR HAVING A DIVIDER WITH AN INVERTER RING ARRANGEMENT
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机译:25%的占空比时钟发生器具有带变频环排列的分频器
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摘要
A receiver device includes an I-Q mixer circuit configured to provide an I-phase signal and a Q-phase signal. The receiver device also includes a first analog-to-digital converter (ADC) circuit configured to digitize the I-phase signal. The receiver device also includes a second ADC circuit configured to digitize the Q-phase signal. The receiver device also includes a 25% duty cycle clock generator configured to provide 25% duty cycle clock signals to the I-Q mixer. The 25% duty cycle clock generator includes a divider circuit with an inverter ring arrangement.
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