A small area DLL-based clock generator using duty cycle controllable cyclic VCOL

摘要

A small area DLL-based clock generator is presented in this work. To reduce the chip area and generate the high-frequency clock, a new cyclic voltage controlled delay line (VCDL) is used. The new VCDL not only provides multiple output frequency but also with duty cycle controllable output. Compared with the traditional VCDL, it has the advantage of the small chip area and low power consumption, and is suitable for use in the frequency multiplier of the digital system. The proposed dock generator has been fabricated in TSMC 0.18 μm complementary metal-oxide-semiconductor process. The core area of the proposed clock generator is 0.018mm~2. The measure root-mean-square and peak-to-peak jitters are 2.66 ps and 24 ps at 500 MHz, respectively. The phase noise is about -106.36dBc/Hz at the offset frequency of 1 MHz. The power dissipation is 7.2 mW for a supply voltage of 1.8 V.