首页> 外国专利> CORELESS ARCHITECTURE AND PROCESSING STRATEGY FOR EMIB-BASED SUBSTRATES WITH HIGH ACCURACY AND HIGH DENSITY

CORELESS ARCHITECTURE AND PROCESSING STRATEGY FOR EMIB-BASED SUBSTRATES WITH HIGH ACCURACY AND HIGH DENSITY

机译:高精确度和高密度的基于EMIB的基体的关联体系结构和处理策略

摘要

Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a plurality of conductive layers over a package substrate. The conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate. The semiconductor package also includes a solder resist that surrounds the FLIs, where the solder resist has a top surface that is substantially coplanar to top surfaces of the FLIs, a bridge coupled directly to the first conductive layer with solder balls, where the first conductive layer is coupled to the FLIs, and a dielectric over the conductive layers, the bridge, and the solder resist of the package substrate. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first conductive layer may include first conductive pads and second conductive pads. The FLIs may include first conductive vias, second conductive vias, diffusion layers, and third conductive pads.
机译:实施例包括半导体封装和形成半导体封装的方法。半导体封装件包括在封装件衬底上方的多个导电层。导电层包括第一导电层和封装基板中的第一级互连(FLI)。半导体封装还包括围绕FLI的阻焊剂,其中阻焊剂具有与FLI的顶表面基本共面的顶表面,通过焊球直接耦合到第一导电层的桥,其中第一导电层耦合到FLI,并在封装衬底的导电层,电桥和阻焊剂上形成电介质。桥可以是嵌入式多管芯互连桥(EMIB)。第一导电层可以包括第一导电垫和第二导电垫。 FLI可以包括第一导电通孔,第二导电通孔,扩散层和第三导电焊盘。

著录项

  • 公开/公告号US2020335443A1

    专利类型

  • 公开/公告日2020-10-22

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201916387167

  • 申请日2019-04-17

  • 分类号H01L23/538;H01L23;H01L23/31;H01L21/48;H01L21/683;

  • 国家 US

  • 入库时间 2022-08-21 11:24:25

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