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DIELECTRIC ISOLATION AND SiGe CHANNEL FORMATION FOR INTEGRATION IN CMOS NANOSHEET CHANNEL DEVICES
DIELECTRIC ISOLATION AND SiGe CHANNEL FORMATION FOR INTEGRATION IN CMOS NANOSHEET CHANNEL DEVICES
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机译:用于CMOS纳米通道器件集成的介电隔离和SiGe通道形成。
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摘要
Method for forming dielectric isolation region and SiGe channels for CMOS integration of nanosheet devices generally includes epitaxially growing a multilayer structure including alternating layers of silicon, silicon germanium having a germanium content of x atomic percent and silicon germanium having a germanium content of at least 25 atomic percent greater than x. The alternating layers can be arranged and selectively patterned to form a nitride dielectric isolation region, silicon nanochannels in the NFET region, and silicon germanium nanochannels in the PFET region.
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