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System on Chip (SOC) Current Profile Model for Integrated Voltage Regulator (IVR) Co-design

机译:集成稳压器(IVR)协同设计的片上系统(SOC)电流分布模型

摘要

A System On Chip (SOC) current profile model for Integrated Voltage Regulator (IVR) co-design may be provided. A first current profile model may be extracted corresponding to an SOC at a first design stage of the SOC. Then it may be determined that an IVR and the SOC pass a first co-simulation based on the extracted first current profile model. Next, a second current profile model may be extracted corresponding to the SOC at a second design stage of the SOC. Then it may be determined that the IVR and the SOC pass a second co-simulation based on the extracted second current profile model. A third current profile model may be extracted corresponding to the SOC at a third design stage of the SOC. Then it may be determined that the IVR and the SOC pass a third co-simulation based on the extracted third current profile model.
机译:可以提供用于集成稳压器(IVR)协同设计的片上系统(SOC)电流分布模型。可以在SOC的第一设计阶段提取与SOC相对应的第一电流分布模型。然后,可以基于所提取的第一当前轮廓模型来确定IVR和SOC通过了第一共同仿真。接下来,可以在SOC的第二设计阶段提取与SOC相对应的第二电流分布模型。然后,可以基于所提取的第二电流轮廓模型来确定IVR和SOC通过了第二共同仿真。可以在SOC的第三设计阶段提取与SOC相对应的第三电流分布模型。然后,可以基于所提取的第三电流分布模型确定IVR和SOC通过了第三协同仿真。

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