The present invention relates to the technical field of secret or secure communication devices. Disclosed is a dual S-core-based 8-bit AES circuit. The circuit is oriented to IoT applications, and compared with conventional 128-bit AES circuits, an 8-bit data path is used to reduce the area and power consumption of the circuit and improve the energy efficiency by making full use of serial processing and partial parallel processing. The circuit comprises a data processing module, a key expansion module, a control module, and a key addition module. The design of dual S-cores enables parallel operation of the data processing module and the key expansion module. The data processing module makes full use of the idle time when the S cores are not invoked by the key expansion module to reduce the number of cycles and improve the throughput. Moreover, a shift operation is realized by a register-to-register mode, which reduces intermediate registers and further reduces the circuit area.
展开▼
