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Dual mode AES implementation to support single and multiple AES operations
Dual mode AES implementation to support single and multiple AES operations
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机译:双模式AES实现可支持单个和多个AES操作
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摘要
An apparatus comprising a mode circuit and an encryption circuit. The mode circuit may be configured to selectively provide register input data on an output signal when in a first mode and memory data on the output signal when in a second mode. The encryption circuit may be configured to interchangeably encrypt/decrypt between the register input data and the memory data.
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