首页> 外国专利> COMMIT LOGIC AND PRECISE EXCEPTIONS IN EXPLICIT DATAFLOW GRAPH EXECUTION ARCHITECTURES

COMMIT LOGIC AND PRECISE EXCEPTIONS IN EXPLICIT DATAFLOW GRAPH EXECUTION ARCHITECTURES

机译:在显式数据流图执行架构中提交逻辑和精确例外

摘要

Systems and methods are disclosed for executing instructions with a block-based processor. Instructions can be executed in any order as their dependencies arrive, but the individual instructions are committed in a serial fashion. Further, exception handling can be performed by storing transient state for an instruction block and resuming by restoring the transient state. This allows programmers to see intermediate state for the instruction block before the subject block has committed. In one examples of the disclosed technology, a method of operating a processor executing a block-based instruction set architecture includes executing at least one instruction encoded for an instruction block, responsive to determining that an individual instruction of the instruction block can commit, advancing a commit frontier for the instruction block to include all instructions in the instruction block that can commit, and committing one or more instructions inside the advanced commit frontier.
机译:公开了用于利用基于块的处理器执行指令的系统和方法。指令可以在依赖项到达时以任何顺序执行,但是各个指令以串行方式提交。此外,可以通过存储指令块的暂态并通过恢复暂态来恢复执行异常处理。这样,程序员可以在提交主题块之前查看指令块的中间状态。在所公开技术的一个示例中,一种操作处理器以执行基于块的指令集架构的处理器的方法包括:响应于确定该指令块的单个指令可以提交,执行,对指令块编码的至少一个指令被执行。指令块的提交边界,以包括该指令块中可以提交的所有指令,并在高级提交边界内提交一个或多个指令。

著录项

  • 公开/公告号WO2020060639A1

    专利类型

  • 公开/公告日2020-03-26

    原文格式PDF

  • 申请/专利权人 MICROSOFT TECHNOLOGY LICENSING LLC;

    申请/专利号WO2019US39596

  • 发明设计人 GUPTA GAGAN;HARPER DAVID T.;

    申请日2019-06-27

  • 分类号G06F9/38;

  • 国家 WO

  • 入库时间 2022-08-21 11:12:29

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