A latch formed from a memory cell includes a clock input port configured to receive a clock signal, complementary first and second data ports, and a latch circuit. The latch circuit has a first and a second inverter. The first inverter has an input connector that is coupled to the first data connector, and the second inverter has an input connector that is coupled to the second data connector. A first pass gate transistor is coupled between an output connection of the second inverter and the first data connection. A second pass gate transistor is coupled between an output connection of the first inverter and the second data connection. The first and second pass gate transistors each have a gate terminal that is coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.
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