ELECTRONIC CIRCUIT WITH SYNCHRONIZED CLOCK DISTRIBUTION

摘要

The present description relates to an electronic circuit comprising: a first integrated circuit chip (ACQ2) comprising a first terminal (CLK_IN) for applying an input clock signal and a second terminal (CLK_OUT) for supplying an output clock signal; and - a second integrated circuit chip (ACQ1) comprising a first terminal (CLK_IN) for applying an input clock signal connected to the second terminal (CLK_OUT) of the first chip (ACQ2) via a connection conductor (122), in which the first chip (ACQ2) comprises a phase compensation circuit (207) configured to supply on its second terminal (CLK_OUT) a clock signal having, with respect to the signal d input clock applied to its first terminal (CLK_IN), a phase advance substantially equal to the phase delay introduced by the connection conductor (122) between the first (ACQ2) and second (ACQ1) chips.