Manufacturing process of a high voltage capacitive element, and corresponding integrated circuit

摘要

An integrated circuit includes a semiconductor substrate (SUB) having a front face (FA), a dielectric region (STI) extending into the substrate from the front face (FA). At least one capacitive element (CHV) comprises, on a surface of the dielectric region (STI) at the level of the front face (FA), a stack of a first conductive region (P0), of a second conductive region (P1 ), and a third conductive region (P2). The second conductive region (P1) is electrically isolated from the first conductive region (P0) by a first dielectric region (DI1) and is electrically isolated from the third conductive region (P2) by a second dielectric region (DI2). Figure for the abstract: Fig 9