Non-volatile memory data bus

摘要

The integrated circuit of non-volatile memory (NVM), comprises a memory plane (PM) organized in rows (RG) and in columns (COL) comprising bit lines (BL), each bit line (BL) comprising amplifiers read (SA) each configured to generate an output signal (SAOUT / SAOUTN) on a read data channel (SABUS / SABUSN). The read data channels (SABUS / SABUSN) run respectively through the memory plane (PM) along each bit line (BL), and each read data channel (SABUS / SABUSN) is connected to all the amplifiers of reading (SA) of the respective bit line (BL). Figure for the abstract: Fig 1