Signal integrity in high-speed applications is dependent on both the underlying device performance and electronic packaging methods. The maturity of chip-on-board (COB) packaging technology using wire bonding makes it a cost beneficial option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance associated with the length of the bond wires that limits the scalability of the system for higher data throughput. A high-speed optical transceiver package according to a first proposed configuration minimizes packaging related parasitic inductance by vertically integrating components using flip-chip bonding. A high-speed optical transceiver package according to a second proposed configuration minimizes packaging related parasitic inductance with horizontal tiling of components using a chip carrier and flip-chip bonding.
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