RÉDUCTION DE PERTURBATION DE PROGRAMME PAR MODIFICATION DE TENSIONS DE LIGNE DE MOTS AU NIVEAU D'UNE INTERFACE DANS UNE PILE À DEUX NIVEAUX APRÈS VÉRIFICATION DE PROGRAMME

摘要

A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a program loop, a different timing is used for decreasing the word line voltages of the interface memory cells compared to the remaining memory cells. In one aspect, the start of the decrease of the word line voltages of the interface memory cells is delayed. In another aspect, the word line voltages of the interface memory cells is decreased to an intermediate level and held for a time period before being decreased further. In another aspect, the word line voltages of the interface memory cells are decreased at a lower rate.