法律状态公告日
法律状态信息
法律状态
2018-08-24
授权
授权
2017-04-12
实质审查的生效 IPC(主分类):G06F12/0884 申请日:20160930
实质审查的生效
2017-03-15
公开
公开
技术领域
本发明属于集成电路设计技术领域,尤其涉及到阵列处理器中4*4阵列处理器簇内分布式存储结构的数据并行访问。
背景技术
随着处理器内部计算核数目增多,集成功能日益复杂,对主存数据访问需求也在逐渐增加,处理速度与存取速度失配所引发的“存储墙”问题也随着工艺的进步而日益严重,并成为制约处理器性能提高的重要因素。为了使处理速度与存储速度之间达到平衡,主流存储结构采用多级Cache技术来缓解不断恶化的“存储墙”问题。然而,多级Cache结构需要附加电路才能完成地址映射,保证数据的一致性。随着集成电路工艺的不断进步,片上集成的处理器核数显著增加,附加电路也会随之增多,采用多级Cache存储结构不仅会增加电路的复杂度,而且会消耗更多的能量。相对于采用多级Cache技术的处理器,现有无Cache结构又面临着访存带宽达不到要求,访问复杂度高、处理器访存灵活性差的问题。为此,研究阵列处理器簇内存储结构,提高访存过程的并行性,并在此基础上缓解处理器与存储器之间的“存储墙”问题,解决多级Cache技术带来的附加电路增多,存储架构复杂,处理器访存灵活性差等问题变得日益迫切。
簇内存储访问行列两级交换电路,充分考虑了数据级并行应用的存储访问特点,采用本地存储单元优先访问策略,并通过“行交换+列交换”的两级交换结构实现了4*4阵列处理器簇内16个处理单元对16个存储块的并行访问。
发明内容
本设计涉及到簇内存储访问行列两级交换电路,目的在于通过行列两级交换结构及本地存储单元优先访问策略,减小数据访问延迟、提高访存带宽、提高资源利用率。
本发明实施例是这样实现的,簇内存储访问行列两级交换电路的功能是接收来自簇内4*4个轻核处理单元PE的存储访问信号,并根据读/写地址进行判断,如果访问本地存储单元,则无阻塞直接访问;如果访问簇内远程其它存储单元,则通过行控制单元和列控制单元进行两级交换实现数据访问;其中本地存储单元指当前PE发起访问请求所对应的存储块;簇内远程其它存储单元指当前PE发起访问请求对应存储块以外的其它存储块。
所述的簇内存储访问行列两级交换电路,由16个分配模块、16个选择模块、4个行控制单元、4个列控制单元构成。
分配模块由2个比较器、1个写分配操作、1个读分配操作和1个读/写反馈产生器构成,主要功能是接收来自处理器的存储访问信号,根据读/写地址idmu_data_raddr / idmu_data_waddr [12:9]位进行判断,如果与本地存储单元编号相同,则为本地读写访问,将该访问信息发送给选择模块,如果与本地存储单元编号不同,则为远程读写访问,将该访问信息发送给行控制单元,并根据接收到的外部请求响应信号及当前请求类型产生输出给处理器的反馈响应信号。
选择模块由1个写数据通路选择、1个读/写使能产生器、1个读/写反馈产生器和1个读数据通路选择构成,主要功能是接收来自分配模块的本地读写访问以及来自列控制单元的远程读写访问,产生输出到本地存储块的存储访问信号,并发回给列控制单元反馈响应信号;当本地读写访问和远程读写访问同时到达时,优先响应本地读写访问。
行控制单元由1个使能选择模块、4个写使能仲裁模块、4个读使能仲裁模块、4个写通路选择模块、4个读通路选择模块和1个读数据选择模块和1个反馈模块构成,主要功能是接收来自16个分配模块的存储访问信号,根据读/写地址idmu_data_raddr / idmu_data_waddr [12:11]位按照轮询算法进行仲裁,将接收到的存储访问信号发送给目的列控制单元,并产生相应的反馈响应信号,其中idmu_data_raddr / idmu_data_waddr [12:11]=00发给0号列控制单元、idmu_data_raddr / idmu_data_waddr [12:11]=01发给1号列控制单元、idmu_data_raddr / idmu_data_waddr [12:11]=10发给2号列控制单元、idmu_data_raddr / idmu_data_waddr [12:11]=11发给3号列控制单元。
列控制单元同行控制单元设计思路相同,但信号的输入来源和输出走向不同,由1个使能选择模块、4个写使能仲裁模块、4个读使能仲裁模块、4个写通路选择模块、4个读通路选择模块和1个读数据选择模块和1个反馈模块构成,主要功能是接收来自4个行控制单元产生的存储访问信号,根据读/写地址idmu_data_raddr / idmu_data_waddr [10:9]位按照轮询算法进行仲裁,将接收到的存储访问信号发送给目的选择模块,并产生相应的反馈响应信号,其中idmu_data_raddr / idmu_data_waddr [10:9]=00发给A号选择模块、idmu_data_raddr / idmu_data_waddr [10:9]=01发给B号选择模块、idmu_data_raddr / idmu_data_waddr [10:9]=10发给C号选择模块、idmu_data_raddr / idmu_data_waddr [10:9]=11发给D号选择模块。
本设计的特点是采用“行交换+列交换”的两级交换结构,完成了4*4阵列处理器对16个分布式存储块的并行全访问,支持本地存储优先访问远程存储次之的优先级策略。
附图说明
图1 簇内存储访问行列两级交换电路结构图;
图2 分配模块电路图;
图3 选择模块电路图;
图4 行控制单元内部结构图;
图5 列控制单元内部结构图;
图6 行/列控制单元中使能选择模块结构图;
图7 行/列控制单元中写使能仲裁模块结构图;
图8 行/列控制单元中读使能仲裁模块结构图;
图9 行/列控制单元中写通路选择模块结构图;
图10行/列控制单元中读通路选择模块结构图;
图11行/列控制单元中读数据选择模块结构图;
图12行/列控制单元中反馈模块结构图。
具体实施方式
本设计的簇内存储访问行列两级交换电路结构图如图1所示,适用于4*4阵列处理器对16个分布式存储块的并行访问,因此需要16组来自处理器端的读/写请求接口信息和16组访问分布式存储块的读/写信息,表1中只列出了1组读/写请求接口信息的情况,簇内其他15组读/写请求接口信息的引脚含义与之相同。
分配模块电路(allot)输入输出接口说明如表2所示;选择模块电路(RAM_arbiter)的输入输出接口说明如表3所示;行控制单元电路(H_top)的输入输出接口说明如表4所示;列控制单元电路(V_top)的输入输出接口说明如表5所示;行/列控制单元中使能选择模块电路(H_en_select)的输入输出接口说明如表6所示;行/列控制单元中写使能仲裁模块电路(H_wr_en_arbiter)的输入输出接口说明如表7所示;行/列控制单元中读使能仲裁模块电路(H_rd_en_arbiter)的输入输出接口说明如表8所示;行/列控制单元中写通路选择模块电路(H_mux4to1_wr)的输入输出接口说明如表9所示;行/列控制单元中读通路选择模块电路(H_mux4to1_rd)的输入输出接口说明如表10所示;行/列控制单元中读数据选择模块电路(H_mux4to1_rdata)的输入输出接口说明如表11所示;行/列控制单元中反馈模块电路(H_mux4to1_rw_ack)的输入输出接口说明如表12所示。
表1,簇内存储访问行列两级交换电路接口信号说明:
表2,分配模块电路(allot)接口信号说明:
表3,选择模块电路(RAM_arbiter)的接口信号说明:
表4,行控制单元电路(H_top)的输入输出接口说明:
(其中H_wr_ 、H_rd_、H_waddr_[12:0]、H_raddr_[12:0]、H_wdata_[31:0]、H_rdata_[31:0]、H_wr_ack、H_rd_ack共有4套端口,序号为0、1、2、3,分别接分配模块A、B、C、D,表格中只列出了其中1套;HV_wr、HV_rd、HV_waddr[12:0]、HV_raddr[12:0]、HV_wdata[31:0]、HV_rdata[31:0]、HV_wr_ack、HV_rd_ack共有4套端口,序号为0、1、2、3,分别列控制单元0、1、2、3,表格中只列出了其中1套。)
表5,列控制单元电路(V_top)的输入输出接口说明:
(其中HV_wr_ 、HV_rd_、HV_waddr_[12:0]、HV_raddr_[12:0]、HV_wdata_[31:0]、HV_rdata_[31:0]、HV_wr_ack、HV_rd_ack共有4套端口,序号为0、1、2、3,分别接行控制单元0、1、2、3,表格中只列出了其中1套;R_wr、R_rd、R_waddr[12:0]、R_raddr[12:0]、R_wdata[31:0]、R_rdata[31:0]、R_wr_ack、R_rd_ack共有4套端口,序号为0、1、2、3,分别选择模块A、B、C、D,表格中只列出了其中1套。)
表6,行/列控制单元中使能选择模块电路(H_en_select)的输入输出接口说明
(其中bus_wr_、bus_rd_、bus_waddr_[12:0]、 bus_raddr_[12:0]共有4套端口,序号分别为0、1、2、3,表格中只列出了其中1套;bus_wr_00、bus_wr_01、bus_wr_02、 bus_wr_03共有4套端口,序号分别为00、01、02、03、10、11、12、13、20、21、22、23、30、31、32、33,表格中只列出了其中1套,bus_rd_00、bus_rd_01、bus_rd_02、bus_rd_03共有4套端口,序号分别为00、01、02、03、10、11、12、13、20、21、22、23、30、31、32、33,表格中只列出了其中1套。)
表7,行/列控制单元中写使能仲裁模块电路(H_wr_en_arbiter)的输入输出接口说明:(其中bus_wr_共有4套端口,序号分别为0、1、2、3,表格中只列出了其中一套。)
表8,行/列控制单元中读使能仲裁模块电路(H_rd_en_arbiter)的输入输出接口说明:(其中bus_ rd _共有4套端口,序号分别为0、1、2、3,表格中只列出了其中一套。)
表9,行/列控制单元中写通路选择模块电路(H_mux4to1_wr)的输入输出接口说明:(其中bus_wr_、bus_waddr_、bus_wdata_共有4套端口,序号分别为0、1、2、3,表格中只列出了其中一套。)
表10,行/列控制单元中读通路选择模块电路(H_mux4to1_rd)的输入输出接口说明:(其中bus_rd_、bus_raddr_共有4套端口,序号分别为0、1、2、3,表格中只列出了其中一套。)
表11,行/列控制单元中读数据选择模块电路(H_mux4to1_rdata)的输入输出接口说明:(其中bus_rdata_、rd_en、bus_rdata共有4套端口,序号分别为0、1、2、3,表格中只列出了其中一套。)
表12,行/列控制单元中反馈模块电路(H_mux4to1_rw_ack)的输入输出接口说明:(其中v_wr_ack、v_rd_ack、bus_wr_ack、bus _rd_ack共有4套端口,序号分别为0、1、2、3,表格中只列出了其中一套。)
电路的Verilog语言描述的核心代码如下:(其中//后面为剩余端口的注释说明)
module top(clk,rst_n,idmu_data_en0,idmu_data_wr_en0,idmu_data_rd_en0,idmu_data_waddr0,
idmu_data_raddr0,idmu_data_wdata0,idmu_data_rdata0,wr_ack0,rd_ack0, ram_en0,wr_enRAM0,rd_enRAM0,wr_addrRAM0,rd_addrRAM0,wr_dataRAM0,rd_dataRAM0,
idmu_data_en15,idmu_data_wr_en15,idmu_data_rd_en15,idmu_data_waddr15,
idmu_data_raddr15,idmu_data_wdata15,idmu_data_rdata15,wr_ack15,rd_ack15, ram_en15,
wr_enRAM15,rd_enRAM15,wr_addrRAM15,rd_addrRAM15,wr_dataRAM15,
rd_dataRAM15);
……
BUS_top BUS_top1_init (.clk(clk),
.rst_n(rst_n),
.b_wr_0(bus_wr0),
.b_rd_0(bus_rd0),
.b_waddr_0(bus_waddr0),
.b_raddr_0(bus_raddr0),
.b_wdata_0(bus_wdata0),
.b_rdata_0(bus_rdata0),
.b_wr_ack0(bus_wr_ack0),
.b_rd_ack0(bus_rd_vld0),
.R_wr_0(wr_enB0),
.R_rd_0(rd_enB0),
.R_waddr_0(wr_addrB0),
.R_raddr_0(rd_addrB0),
.R_wdata_0(wr_dataB0),
.R_rdata_0(rd_dataB0),
.R_wr_ack0(wr_ackB0),
.R_rd_ack0(rd_ackB0));
...... //(此处省略的代码为该模块剩下的15组信号,接口分别为
.b_wr_1~15(bus_wr1~15), .b_rd_1~15 (bus_rd1~15), .b_waddr_1~14(bus_waddr1~15),
.b_raddr_1~15 (bus_raddr1~15), .b_wdata_1~15 (bus_wdata1~15),.b_rdata_1~15 (bus_rdata1~15),
.b_wr_ack1~15 (bus_wr_ack1~15),.b_rd_ack1~15 (bus_rd_vld1~15),
.R_wr_1~15 (wr_enB1~15), .R_rd_0(rd_enB1~15), .R_waddr_1~15 (wr_addrB1~15),
.R_raddr_1~15 (rd_addrB1~15), .R_wdata_1~15 (wr_dataB1~15),
.R_rdata_1~15 (rd_dataB1~15), .R_wr_ack1~15 (wr_ackB1~15),.R_rd_ack1~15 (rd_ackB1~15).)
……
RAM_allot_top #(.id(4'd0)) RAM_allot_top0_init(.clk(clk),
.rst_n(rst_n),
.wr_ack(wr_ack0),
.rd_ack(rd_ack0),
.idmu_data_en(idmu_data_en0),
.idmu_data_wr_en(idmu_data_wr_en0),
.idmu_data_rd_en(idmu_data_rd_en0),
.idmu_data_waddr(idmu_data_waddr0),
.idmu_data_raddr(idmu_data_raddr0),
.idmu_data_wdata(idmu_data_wdata0),
.idmu_data_rdata(idmu_data_rdata0),
.bus_wr(bus_wr0),
.bus_rd(bus_rd0),
.bus_waddr(bus_waddr0),
.bus_raddr(bus_raddr0),
.bus_wdata(bus_wdata0),
.bus_rdata(bus_rdata0),
.bus_wr_ack(bus_wr_ack0),
.bus_rd_vld(bus_rd_vld0),
.wr_enB(wr_enB0),
.rd_enB(rd_enB0),
.wr_addrB(wr_addrB0),
.rd_addrB(rd_addrB0),
.wr_dataB(wr_dataB0),
.rd_dataB(rd_dataB0),
.wr_ackB(wr_ackB0),
.rd_ackB(rd_ackB0),
.ram_en(ram_en0),
.wr_enRAM(wr_enRAM0),
.rd_enRAM(rd_enRAM0),
.wr_addrRAM(wr_addrRAM0),
.rd_addrRAM(rd_addrRAM0),
.wr_dataRAM(wr_dataRAM0),
.rd_dataRAM(rd_dataRAM0));
//(此处省略的代码为剩下的15个实例化模块信号,模块编号分别为1~15,所传参数分别为1~15,主要接口分别为
.wr_ack(wr_ack1~15),.rd_ack(rd_ack1~15),.idmu_data_en(idmu_data_en1~15),
.idmu_data_wr_en(idmu_data_wr_en1~15),.idmu_data_rd_en(idmu_data_rd_en1~15),
.idmu_data_waddr(idmu_data_waddr1~15),.idmu_data_raddr(idmu_data_raddr1~15),
.idmu_data_wdata(idmu_data_wdata1~15),.idmu_data_rdata(idmu_data_rdata1~15),
.bus_wr(bus_wr1~15),.bus_rd(bus_rd1~15), .bus_waddr(bus_waddr1~15),
.bus_raddr(bus_raddr1~15),.bus_wdata(bus_wdata1~15),.bus_rdata(bus_rdata1~15),
.bus_wr_ack(bus_wr_ack1~15),.bus_rd_vld(bus_rd_vld1~15),
.wr_enB(wr_enB1~15),.rd_enB(rd_enB1~15),.wr_addrB(wr_addrB1~15),
.rd_addrB(rd_addrB1~15),.wr_dataB(wr_dataB1~15),.rd_dataB(rd_dataB1~15),
.wr_ackB(wr_ackB1~15),.rd_ackB(rd_ackB1~15), .ram_en(ram_en1~15),
.wr_enRAM(wr_enRAM1~15),.rd_enRAM(rd_enRAM1~15),
.wr_addrRAM(wr_addrRAM1~15),.rd_addrRAM(rd_addrRAM1~15),
.wr_dataRAM(wr_dataRAM1~15),.rd_dataRAM(rd_dataRAM1~15).)
endmodule
module RAM_allot_top(clk,rst_n,idmu_data_en,idmu_data_wr_en,idmu_data_rd_en,idmu_data_waddr,
idmu_data_raddr,idmu_data_wdata,idmu_data_rdata,wr_ack,rd_ack,
bus_wr,bus_rd,bus_waddr,bus_raddr,bus_wdata,bus_rdata,bus_wr_ack,bus_rd_vld,
wr_enB,rd_enB,wr_addrB,rd_addrB,wr_dataB,rd_dataB,wr_ackB,rd_ackB, ram_en,wr_enRAM,rd_enRAM,wr_addrRAM,rd_addrRAM,wr_dataRAM,
rd_dataRAM);
……
parameter id = 4'b0001;
allot #(.local_id(id)) allot_init (.clk(clk),
.rst_n(rst_n),
.idmu_data_en(idmu_data_en),
.idmu_data_wr_en(idmu_data_wr_en),
.idmu_data_rd_en(idmu_data_rd_en),
.idmu_data_waddr(idmu_data_waddr),
.idmu_data_raddr(idmu_data_raddr),
.idmu_data_wdata(idmu_data_wdata),
.idmu_data_rdata(idmu_data_rdata),
.wr_ack(wr_ack),
.rd_ack(rd_ack),
.ram_wr(ram_wr),
.ram_rd(ram_rd),
.ram_waddr(ram_waddr),
.ram_raddr(ram_raddr),
.ram_wdata(ram_wdata),
.ram_rdata(ram_rdata),
.bus_wr(bus_wr),
.bus_rd(bus_rd),
.bus_waddr(bus_waddr),
.bus_raddr(bus_raddr),
.bus_wdata(bus_wdata),
.bus_rdata(bus_rdata),
.bus_wr_ack(bus_wr_ack),
.bus_rd_vld(bus_rd_vld));
RAM_arbiter ram_arbiter_init (.clk(clk),
.rst_n(rst_n),
.ram_en(ram_en),
.wr_enA(ram_wr),
.wr_addrA(ram_waddr),
.wr_dataA(ram_wdata),
.rd_enA(ram_rd),
.rd_addrA(ram_raddr),
.rd_dataA(ram_rdata),
.wr_enB(wr_enB),
.wr_addrB(wr_addrB),
.wr_dataB(wr_dataB),
.wr_ackB(wr_ackB),
.rd_enB(rd_enB),
.rd_addrB(rd_addrB),
.rd_dataB(rd_dataB),
.rd_ackB(rd_ackB),
.wr_enRAM(wr_enRAM),
.wr_addrRAM(wr_addrRAM),
.wr_dataRAM(wr_dataRAM),
.rd_enRAM(rd_enRAM),
.rd_addrRAM(rd_addrRAM),
.rd_dataRAM(rd_dataRAM));
endmodule
module allot(clk,rst_n,idmu_data_en,idmu_data_wr_en,idmu_data_rd_en,idmu_data_waddr,
idmu_data_wdata,idmu_data_raddr,idmu_data_rdata,wr_ack,rd_ack,
ram_wr,ram_rd,ram_waddr,ram_raddr,ram_wdata,ram_rdata,
bus_wr,bus_rd,bus_waddr,bus_raddr,bus_wdata,bus_rdata,
bus_wr_ack,bus_rd_vld);
……
parameter local_id = 4'b0001;
assign data_wr = idmu_data_en & idmu_data_wr_en ;
assign data_rd = idmu_data_en & idmu_data_rd_en;
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
data_wr_flag <= 1'b0;
data_wdata <= 32'd0;
data_waddr <= 16'd0;
end
else if(wr_ack)begin
data_wr_flag <= 1'b0;
data_wdata <= 32'd0;
data_waddr <= 16'd0;
end
else if(data_wr == 1'b1)begin
data_wr_flag <= 1'b1;
data_wdata <= idmu_data_wdata;
data_waddr <= idmu_data_waddr;
end
else begin
data_wr_flag <= data_wr_flag;
data_wdata <= data_wdata;
data_waddr <= data_waddr;
end
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
data_rd_flag <= 1'b0;
data_raddr <= 16'd0;
end
else if(rd_ack == 1'b1)begin
data_rd_flag <= 1'b0;
data_raddr <= 16'd0;
end
else if(data_rd == 1'b1)begin
data_rd_flag <= 1'b1;
data_raddr <= idmu_data_raddr;
end
else begin
data_rd_flag <= data_rd_flag;
data_raddr <= data_raddr;
end
end
assign ram_wr = data_wr&(idmu_data_waddr[12:9] == local_id);
assign ram_rd = data_rd&(idmu_data_raddr[12:9] == local_id);
assign bus_wr = (data_wr&(idmu_data_waddr[12:9]!= local_id))||(data_wr_flag &(data_waddr[12:9]!= local_id));
assign bus_rd = (data_rd&(idmu_data_raddr[12:9]!= local_id))||(data_rd_flag&(rd_ack==1'b0)& (data_raddr[12:9]!=local_id));
assign ram_wdata = idmu_data_wdata ;
assign bus_wdata = (data_wr == 1'b1) ? idmu_data_wdata : ( data_wr_flag == 1'b1 ) ? data_wdata : 32'd0;
assign wr_ack = bus_wr_ack | ram_wr;
assign ram_waddr = idmu_data_waddr ;
assign ram_raddr = idmu_data_raddr ;
assign bus_waddr = (data_wr == 1'b1) ? idmu_data_waddr : (data_wr_flag == 1'b1 ) ? data_waddr : 16'd0;
assign bus_raddr = (data_rd == 1'b1) ? idmu_data_raddr : (data_rd_flag == 1'b1 & (rd_ack == 1'b0)) ? data_raddr : 16'd0;
always@( posedge clk or negedge rst_n)begin
if(~rst_n)ram_rd1 <= 1'd0;
else ram_rd1 <= ram_rd;
end
assign idmu_data_rdata=(ram_rd1==1'd1)?ram_rdata:((ram_rd1==1'd0)&(bus_rd_vld == 1'd1)) ?
bus_rdata :32'd0;
assign rd_ack = ram_rd1 | bus_rd_vld;
endmodule
module RAM_arbiter (clk,rst_n,ram_en,wr_enA,wr_enB,wr_addrA,wr_addrB,wr_dataA,
wr_dataB,wr_ackB, rd_enA,rd_enB,rd_addrA,rd_addrB,rd_dataA,rd_dataB,rd_ackB,
wr_enRAM,rd_enRAM,wr_addrRAM,rd_addrRAM,wr_dataRAM,rd_dataRAM);
……
assign ram_en = wr_enRAM | rd_enRAM;
assign wr_enRAM = wr_enA | wr_enB ;
assign wr_ackB = ~wr_enA & wr_enB;
assign wr_addrRAM = wr_enA ? wr_addrA[8:0] : wr_addrB[8:0] ;
assign wr_dataRAM = wr_enA ? wr_dataA : wr_dataB ;
assign rd_enRAM = rd_enA | rd_enB ;
assign rd_ackB = ~rd_enA_reg & rd_enB_reg;
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
rd_enA_reg <= 1'b0;
rd_enB_reg <= 1'b0;
end
else begin
rd_enA_reg <= rd_enA;
rd_enB_reg <= rd_enB;
end
assign rd_addrRAM = rd_enA ? rd_addrA[8:0] : rd_addrB[8:0] ;
assign rd_dataB = rd_dataRAM;
assign rd_dataA = rd_dataRAM;
endmodule
moduleBUS_top(clk,rst_n,b_wr_0,b_rd_0,b_waddr_0,b_raddr_0,b_wdata_0,b_rdata_0,
b_wr_ack0,b_rd_ack0,R_wr_0,R_rd_0,R_waddr_0,R_raddr_0,R_wdata_0,
R_rdata_0,R_wr_ack0,R_rd_ack0,
b_wr_15, b_rd_15,b_waddr_15,b_raddr_15,b_wdata_15,b_rdata_15,
b_wr_ack15,b_rd_ack15,R_wr_15,R_rd_15,R_waddr_15,R_raddr_15,
R_wdata_15,R_rdata_15, R_wr_ack15,R_rd_ack15);
……
H_topH_top0(.clk(clk),
.rst_n(rst_n),
.H_wr_0 (b_wr_0),
.H_rd_0 (b_rd_0),
.H_waddr_0(b_waddr_0),
.H_raddr_0(b_raddr_0),
.H_wdata_0(b_wdata_0),
.H_rdata_0(b_rdata_0),
.H_wr_ack0(b_wr_ack0),
.H_rd_ack0(b_rd_ack0),
.H_wr_1 (b_wr_4),
.H_rd_1 (b_rd_4),
.H_waddr_1(b_waddr_4),
.H_raddr_1(b_raddr_4),
.H_wdata_1(b_wdata_4),
.H_rdata_1(b_rdata_4),
.H_wr_ack1(b_wr_ack4),
.H_rd_ack1 (b_rd_ack4),
.H_wr_2 (b_wr_8),
.H_rd_2 (b_rd_8),
.H_waddr_2(b_waddr_8),
.H_raddr_2(b_raddr_8),
.H_wdata_2(b_wdata_8),
.H_rdata_2(b_rdata_8),
.H_wr_ack2(b_wr_ack8),
.H_rd_ack2(b_rd_ack8),
.H_wr_3 (b_wr_12),
.H_rd_3 (b_rd_12),
.H_waddr_3(b_waddr_12),
.H_raddr_3(b_raddr_12),
.H_wdata_3(b_wdata_12),
.H_rdata_3(b_rdata_12),
.H_wr_ack3(b_wr_ack12),
.H_rd_ack3(b_rd_ack12),
.HV_wr0 (HV_wr_0A),
.HV_rd0 (HV_rd_0A),
.HV_waddr0 (HV_waddr_0A),
.HV_raddr0 (HV_raddr_0A),
.HV_wdata0 (HV_wdata_0A),
.HV_rdata0 (HV_rdata_0A),
.HV_wr_ack0(HV_wr_ack0A),
.HV_rd_ack0(HV_rd_ack0A),
.HV_wr1 (HV_wr_1A),
.HV_rd1 (HV_rd_1A),
.HV_waddr1 (HV_waddr_1A),
.HV_raddr1 (HV_raddr_1A),
.HV_wdata1 (HV_wdata_1A),
.HV_rdata1 (HV_rdata_1A),
.HV_wr_ack1(HV_wr_ack1A),
.HV_rd_ack1(HV_rd_ack1A),
.HV_wr2 (HV_wr_2A),
.HV_rd2 (HV_rd_2A),
.HV_waddr2 (HV_waddr_2A),
.HV_raddr2 (HV_raddr_2A),
.HV_wdata2 (HV_wdata_2A),
.HV_rdata2 (HV_rdata_2A),
.HV_wr_ack2(HV_wr_ack2A),
.HV_rd_ack2(HV_rd_ack2A),
.HV_wr3 (HV_wr_3A),
.HV_rd3 (HV_rd_3A),
.HV_waddr3 (HV_waddr_3A),
.HV_raddr3 (HV_raddr_3A),
.HV_wdata3 (HV_wdata_3A),
.HV_rdata3 (HV_rdata_3A),
.HV_wr_ack3(HV_wr_ack3A),
.HV_rd_ack3(HV_rd_ack3A));
...... //(此处省略的代码为剩下的3个实例化模块信号,模块编号分别为1、2、3,主要接口分别为.H_wr_0 (b_wr_1、2、3),.H_rd_0 (b_rd_1、2、3),.H_waddr_0(b_waddr_1、2、3),
.H_raddr_0(b_raddr_1、2、3),.H_wdata_0(b_wdata_1、2、3),.H_rdata_0(b_rdata_1、2、3),
.H_wr_ack0(b_wr_ack1、2、3),.H_rd_ack0(b_rd_ack1、2、3),
.H_wr_1(b_wr_5、6、7),.H_rd_1(b_rd_5、6、7),.H_waddr_1(b_waddr_5、6、7),
.H_raddr_1(b_raddr_5、6、7),.H_wdata_1(b_wdata_5、6、7),.H_rdata_1(b_rdata_5、6、7),
.H_wr_ack1(b_wr_ack5、6、7),.H_rd_ack1(b_rd_ack5、6、7),
.H_wr_2 (b_wr_9、10、11),.H_rd_2 (b_rd_9、10、11),.H_waddr_2(b_waddr_9、10、11),
.H_raddr_2(b_raddr_9、10、11),.H_wdata_2(b_wdata_9、10、11),
.H_rdata_2(b_rdata_9、10、11),.H_wr_ack2(b_wr_ack9、10、11),
.H_rd_ack2(b_rd_ack9、10、11),.H_wr_3 (b_wr_13、14、15),.H_rd_3 (b_rd_13、14、15),
.H_waddr_3(b_waddr_13、14、15),.H_raddr_3(b_raddr_13、14、15),
.H_wdata_3(b_wdata_13、14、15),.H_rdata_3(b_rdata_13、14、15),
.H_wr_ack3(b_wr_ack13、14、15),.H_rd_ack3(b_rd_ack13、14、15),
.HV_wr0 (HV_wr_0B、0C、0D),.HV_rd0 (HV_rd_0B、0C、0D),
.HV_waddr0 (HV_waddr_0B、0C、0D),.HV_raddr0 (HV_raddr_0B、0C、0D),
.HV_wdata0 (HV_wdata_0B、0C、0D),.HV_rdata0 (HV_rdata_0B、0C、0D),
.HV_wr_ack0(HV_wr_ack0B、0C、0D),.HV_rd_ack0(HV_rd_ack0B、0C、0D),
.HV_wr1 (HV_wr_1B、1C、1D),.HV_rd1 (HV_rd_1B、1C、1D),
.HV_waddr1 (HV_waddr_1B、1C、1D),.HV_raddr1 (HV_raddr_1B、1C、1D),
.HV_wdata1 (HV_wdata_1B、1C、1D),.HV_rdata1 (HV_rdata_1B、1C、1D),
.HV_wr_ack1(HV_wr_ack1B、1C、1D),.HV_rd_ack1(HV_rd_ack1B、1C、1D),
.HV_wr2 (HV_wr_2B、2C、2D),.HV_rd2 (HV_rd_2B、2C、2D),
.HV_waddr2 (HV_waddr_2B、2C、2D),.HV_raddr2 (HV_raddr_2B、2C、2D),
.HV_wdata2 (HV_wdata_2B、2C、2D),.HV_rdata2 (HV_rdata_2B、2C、2D),
.HV_wr_ack2(HV_wr_ack2B、2C、2D),.HV_rd_ack2(HV_rd_ack2B、2C、2D),
.HV_wr3 (HV_wr_3B、3C、3D),.HV_rd3 (HV_rd_3B、3C、3D),
.HV_waddr3 (HV_waddr_3B、3C、3D),.HV_raddr3 (HV_raddr_3B、3C、3D),
.HV_wdata3 (HV_wdata_3B、3C、3D),.HV_rdata3 (HV_rdata_3B、3C、3D),
.HV_wr_ack3(HV_wr_ack3B、3C、3D),.HV_rd_ack3(HV_rd_ack3B、3C、3D).)
V_top V_top0(.clk(clk),
.rst_n(rst_n),
.HV_wr_0 (HV_wr_0A),
.HV_rd_0 (HV_rd_0A),
.HV_waddr_0(HV_waddr_0A),
.HV_raddr_0(HV_raddr_0A),
.HV_wdata_0(HV_wdata_0A),
.HV_rdata_0(HV_rdata_0A),
.HV_wr_ack0(HV_wr_ack0A),
.HV_rd_ack0(HV_rd_ack0A),
.HV_wr_1 (HV_wr_0B),
.HV_rd_1 (HV_rd_0B),
.HV_waddr_1(HV_waddr_0B),
.HV_raddr_1(HV_raddr_0B),
.HV_wdata_1(HV_wdata_0B),
.HV_rdata_1(HV_rdata_0B),
.HV_wr_ack1(HV_wr_ack0B),
.HV_rd_ack1(HV_rd_ack0B),
.HV_wr_2 (HV_wr_0C),
.HV_rd_2 (HV_rd_0C),
.HV_waddr_2(HV_waddr_0C),
.HV_raddr_2(HV_raddr_0C),
.HV_wdata_2(HV_wdata_0C),
.HV_rdata_2(HV_rdata_0C),
.HV_wr_ack2(HV_wr_ack0C),
.HV_rd_ack2(HV_rd_ack0C),
.HV_wr_3 (HV_wr_0D),
.HV_rd_3 (HV_rd_0D),
.HV_waddr_3(HV_waddr_0D),
.HV_raddr_3(HV_raddr_0D),
.HV_wdata_3(HV_wdata_0D),
.HV_rdata_3(HV_rdata_0D),
.HV_wr_ack3(HV_wr_ack0D),
.HV_rd_ack3(HV_rd_ack0D),
.R_wr0 (R_wr_0),
.R_rd0 (R_rd_0),
.R_waddr0 (R_waddr_0),
.R_raddr0 (R_raddr_0),
.R_wdata0 (R_wdata_0),
.R_rdata0 (R_rdata_0),
.R_wr_ack0(R_wr_ack0),
.R_rd_ack0(R_rd_ack0),
.R_wr1 (R_wr_1),
.R_rd1 (R_rd_1),
.R_waddr1 (R_waddr_1),
.R_raddr1 (R_raddr_1),
.R_wdata1 (R_wdata_1),
.R_rdata1 (R_rdata_1),
.R_wr_ack1(R_wr_ack1),
.R_rd_ack1(R_rd_ack1),
.R_wr2 (R_wr_2),
.R_rd2 (R_rd_2),
.R_waddr2 (R_waddr_2),
.R_raddr2 (R_raddr_2),
.R_wdata2 (R_wdata_2),
.R_rdata2 (R_rdata_2),
.R_wr_ack2(R_wr_ack2),
.R_rd_ack2(R_rd_ack2),
.R_wr3 (R_wr_3),
.R_rd3 (R_rd_3),
.R_waddr3 (R_waddr_3),
.R_raddr3 (R_raddr_3),
.R_wdata3 (R_wdata_3),
.R_rdata3 (R_rdata_3),
.R_wr_ack3(R_wr_ack3),
.R_rd_ack3(R_rd_ack3));
...... //(此处省略的代码为剩下的3个实例化模块信号,模块编号分别为1、2、3,主要接口分别为.HV_wr_0 (HV_wr_1A、2A、3A),.HV_rd_0 (HV_rd_1A、2A、3A),
.HV_waddr_0(HV_waddr_1A、2A、3A),.HV_raddr_0(HV_raddr_1A、2A、3A),
.HV_wdata_0(HV_wdata_1A、2A、3A),.HV_rdata_0(HV_rdata_1A、2A、3A),
.HV_wr_ack0(HV_wr_ack1A、2A、3A),.HV_rd_ack0(HV_rd_ack1A、2A、3A),
.HV_wr_1 (HV_wr_1B、2B、3B),.HV_rd_1 (HV_rd_1B、2B、3B),
.HV_waddr_1(HV_waddr_1B、2B、3B),.HV_raddr_1(HV_raddr_1B、2B、3B),
.HV_wdata_1(HV_wdata_1B、2B、3B),.HV_rdata_1(HV_rdata_1B、2B、3B),
.HV_wr_ack1(HV_wr_ack1B、2B、3B),.HV_rd_ack1(HV_rd_ack1B、2B、3B),
.HV_wr_2 (HV_wr_1C、2C、3C),.HV_rd_2 (HV_rd_1C、2C、3C),
.HV_waddr_2(HV_waddr_1C、2C、3C),.HV_raddr_2(HV_raddr_1C、2C、3C),
.HV_wdata_2(HV_wdata_1C、2C、3C),.HV_rdata_2(HV_rdata_1C、2C、3C),
.HV_wr_ack2(HV_wr_ack1C、2C、3C),.HV_rd_ack2(HV_rd_ack1C、2C、3C),
.HV_wr_3 (HV_wr_1D、2D、3D),.HV_rd_3 (HV_rd_1D、2D、3D),
.HV_waddr_3(HV_waddr_1D、2D、3D),.HV_raddr_3(HV_raddr_1D、2D、3D),
.HV_wdata_3(HV_wdata_1D、2D、3D),.HV_rdata_3(HV_rdata_1D、2D、3D),
.HV_wr_ack3(HV_wr_ack1D、2D、3D),.HV_rd_ack3(HV_rd_ack1D、2D、3D),
.R_wr0 (R_wr_4、8、12),.R_rd0 (R_rd_4、8、12),
.R_waddr0 (R_waddr_4、8、12),.R_raddr0 (R_raddr_4、8、12),
.R_wdata0 (R_wdata_4、8、12),.R_rdata0 (R_rdata_4、8、12),
.R_wr_ack0(R_wr_ack4、8、12),.R_rd_ack0(R_rd_ack4、8、12),
.R_wr1 (R_wr_5、9、13),.R_rd1 (R_rd_5、9、13),
.R_waddr1 (R_waddr_5、9、13),.R_raddr1 (R_raddr_5、9、13),
.R_wdata1 (R_wdata_5、9、13),.R_rdata1 (R_rdata_5、9、13),
.R_wr_ack1(R_wr_ack5、9、13),.R_rd_ack1(R_rd_ack5、9、13),
.R_wr2(R_wr_6、10、14),.R_rd2(R_rd_6、10、14),
.R_waddr2 (R_waddr_6、10、14),.R_raddr2 (R_raddr_6、10、14),
.R_wdata2 (R_wdata_6、10、14),.R_rdata2 (R_rdata_6、10、14),
.R_wr_ack2(R_wr_ack6、10、14),.R_rd_ack2(R_rd_ack6、10、14),
.R_wr3 (R_wr_7、11、15),.R_rd3 (R_rd_7、11、15),
.R_waddr3 (R_waddr_7、11、15),.R_raddr3 (R_raddr_7、11、15),
.R_wdata3 (R_wdata_7、11、15),.R_rdata3 (R_rdata_7、11、15),
.R_wr_ack3(R_wr_ack7、11、15),.R_rd_ack3(R_rd_ack7、11、15).)
endmodule
module H_top(clk,rst_n,H_wr_0,H_rd_0,H_waddr_0,H_raddr_0,H_wdata_0,H_rdata_0,
H_wr_ack0,H_rd_ack0, HV_wr0,HV_rd0,HV_waddr0,HV_raddr0,HV_wdata0,
HV_rdata0,HV_wr_ack0,HV_rd_ack0,
……
H_wr_3,H_rd_3,H_waddr_3,H_raddr_3,H_wdata_3,H_rdata_3,H_wr_ack3,
H_rd_ack3,HV_wr3,HV_rd3,HV_waddr3,HV_raddr3,HV_wdata3,HV_rdata3,
HV_wr_ack3,HV_rd_ack3);
……
H_en_select H_en_select(.bus_wr_0(H_wr_0),
.bus_rd_0(H_rd_0),
.bus_waddr_0(H_waddr_0),
.bus_raddr_0(H_raddr_0),
.bus_wr_00(wr00),
.bus_wr_01(wr01),
.bus_wr_02(wr02),
.bus_wr_03(wr03),
.bus_rd_00(rd00),
.bus_rd_01(rd01),
.bus_rd_02(rd02),
.bus_rd_03(rd03));
...... //(此处省略的代码为该模块剩下的3组信号,接口分别为
.bus_wr_1(H_wr_1、2、3),.bus_rd_1(H_rd_1、2、3),
.bus_waddr_1(H_waddr_1、2、3),.bus_raddr_1(H_raddr_1、2、3).
.bus_wr_10(wr10),.bus_wr_11(wr11),.bus_wr_12(wr12),.bus_wr_13(wr13),
.bus_wr_20(wr20),.bus_wr_21(wr21),.bus_wr_22(wr22),.bus_wr_23(wr23),
.bus_wr_30(wr30),.bus_wr_31(wr31),.bus_wr_32(wr32),.bus_wr_33(wr33),
.bus_rd_10(rd10),.bus_rd_11(rd11),.bus_rd_12(rd12),.bus_rd_13(rd13),
.bus_rd_20(rd20),.bus_rd_21(rd21),.bus_rd_22(rd22),.bus_rd_23(rd23),
.bus_rd_30(rd30),.bus_rd_31(rd31),.bus_rd_32(rd32),.bus_rd_33(rd33).)
H_wr_en_arbiter H_wr_en_arbiter0(.wr_ack(HV_wr_ack0),
.clk(clk),
.rst_n(rst_n),
.bus_wr_0(wr00),
.bus_wr_1(wr10),
.bus_wr_2(wr20),
.bus_wr_3(wr30),
.wr_en(wr0));
...... //(此处省略的代码为该模块剩下的3组信号,接口分别为
.bus_wr_0(wr01、02、03), .bus_wr_1(wr11、12、13),.bus_wr_2(wr21、22、23),
.bus_wr_3(wr31、32、33),.wr_en(wr1、2、3) .)
H_rd_en_arbiter H_rd_en_arbiter0(.rd_ack(HV_rd_ack0),
.clk(clk),
.rst_n(rst_n),
.bus_rd_0(rd00),
.bus_rd_1(rd10),
.bus_rd_2(rd20),
.bus_rd_3(rd30),
.rd_en(rd0));
...... //(此处省略的代码为该模块剩下的3组信号,接口分别为
.bus_rd_0(wr01、02、03), .bus_rd_1(wr11、12、13),.bus_rd_2(wr21、22、23),
.bus_rd_3(wr31、32、33),.rd_en(wr1、2、3). )
H_mux4to1_wr H_mux4to1_wr0 (.bus_wr_0(H_wr_0),
.bus_wr_1(H_wr_1),
.bus_wr_2(H_wr_2),
.bus_wr_3(H_wr_3),
.bus_waddr_0(H_waddr_0),
.bus_waddr_1(H_waddr_1),
.bus_waddr_2(H_waddr_2),
.bus_waddr_3(H_waddr_3),
.bus_wdata_0(H_wdata_0),
.bus_wdata_1(H_wdata_1),
.bus_wdata_2(H_wdata_2),
.bus_wdata_3(H_wdata_3),
.wr_en(wr0),
.bus_wr(HV_wr0),
.bus_waddr(HV_waddr0),
.bus_wdata(HV_wdata0));
...... //(此处省略的代码为剩下的3个实例化模块信号,模块编号分别为1、2、3,主要接口分别为.bus_wr_0(H_wr_0),.bus_wr_1(H_wr_1),.bus_wr_2(H_wr_2),.bus_wr_3(H_wr_3),
.bus_waddr_0(H_waddr_0),.bus_waddr_1(H_waddr_1),.bus_waddr_2(H_waddr_2),
.bus_waddr_3(H_waddr_3),.bus_wdata_0(H_wdata_0),.bus_wdata_1(H_wdata_1),
.bus_wdata_2(H_wdata_2),.bus_wdata_3(H_wdata_3),.wr_en(wr1、2、3),
.bus_wr(HV_wr1、2、3),.bus_waddr(HV_waddr1、2、3),.bus_wdata(HV_wdata1、2、3).)
H_mux4to1_rd H_mux4to1_rd0(.bus_rd_0(H_rd_0),
.bus_rd_1(H_rd_1),
.bus_rd_2(H_rd_2),
.bus_rd_3(H_rd_3),
.bus_raddr_0(H_raddr_0),
.bus_raddr_1(H_raddr_1),
.bus_raddr_2(H_raddr_2),
.bus_raddr_3(H_raddr_3),
.rd_en(rd0),
.bus_rd(HV_rd0),
.bus_raddr(HV_raddr0));
...... //(此处省略的代码为剩下的3个实例化模块信号,模块编号分别为1、2、3,主要接口分别为.bus_rd_0(H_rd_0),.bus_rd_1(H_rd_1),.bus_rd_2(H_rd_2),.bus_rd_3(H_rd_3),
.bus_raddr_0(H_raddr_0),.bus_raddr_1(H_raddr_1),.bus_raddr_2(H_raddr_2),
.bus_raddr_3(H_raddr_3),
.rd_en(rd1、2、3),.bus_rd(HV_rd1、2、3),.bus_raddr(HV_raddr1、2、3).)
H_mux4to1_rdata H_mux4to1_rdata(.clk(clk),
.rst_n(rst_n),
.bus_rdata_0(HV_rdata0),
.rd_en0(rd0),
.bus_rdata0(H_rdata_0));
...... //(此处省略的代码为该模块剩下的3组信号,接口分别为
.bus_rdata_1(HV_rdata1、2、3), .rd_en1(rd1、2、3), .bus_rdata1(H_rdata_1、2、3).)
H_mux4to1_rw_ack H_mux4to1_rw_ack(.clk(clk),
.rst_n(rst_n),
.wr_en0(wr0),
.rd_en0(rd0),
.v_wr_ack0(HV_wr_ack0),
.v_rd_ack0(HV_rd_ack0),
.bus_wr_ack0(H_wr_ack0),
.bus_rd_ack0(H_rd_ack0));
...... //(此处省略的代码为该模块剩下的3组信号,接口分别为.wr_en1(wr1、2、3),
.rd_en1(rd1、2、3),.v_wr_ack1(HV_wr_ack1、2、3),.v_rd_ack1(HV_rd_ack1、2、3),
.bus_wr_ack1(H_wr_ack1、2、3), .bus_rd_ack1(H_rd_ack1、2、3).)
endmodule
module V_top (clk,rst_n,HV_wr_0,HV_rd_0,HV_waddr_0,HV_raddr_0,HV_wdata_0,
HV_rdata_0,HV_wr_ack0,HV_rd_ack0, R_wr0,R_rd0,R_waddr0,R_raddr0,
R_wdata0,R_rdata0,R_wr_ack0,R_rd_ack0,
……
HV_wr_3,HV_rd_3,HV_waddr_3,HV_raddr_3,HV_wdata_3,
HV_rdata_3,HV_wr_ack3,HV_rd_ack3,R_wr3,R_rd3,R_waddr3,
R_raddr3,R_wdata3,R_rdata3,R_wr_ack3,R_rd_ack3);
……
H_en_select H_en_select(.bus_wr_0(HV_wr_0),
.bus_rd_0(HV_rd_0),
.bus_waddr_0(HV_waddr_0),
.bus_raddr_0(HV_raddr_0),
.bus_wr_00(wr00),
.bus_wr_01(wr01),
.bus_wr_02(wr02),
.bus_wr_03(wr03),
.bus_rd_00(rd00),
.bus_rd_01(rd01),
.bus_rd_02(rd02),
.bus_rd_03(rd03),
...... //(此处省略的代码为该模块剩下的3组信号,接口分别为
.bus_wr_1(HV_wr_1、2、3),.bus_rd_1(HV_rd_1、2、3),
.bus_waddr_1(HV_waddr_1、2、3),.bus_raddr_1(HV_raddr_1、2、3).
.bus_wr_10(wr10) ,.bus_wr_11(wr11) ,.bus_wr_12(wr12) ,.bus_wr_13(wr13) ,
.bus_wr_20(wr20) ,.bus_wr_21(wr21) ,.bus_wr_22(wr22) ,.bus_wr_23(wr23) ,
.bus_wr_30(wr30) ,.bus_wr_31(wr31) ,.bus_wr_32(wr32) ,.bus_wr_33(wr33),
.bus_rd_10(rd10),.bus_rd_11(rd11),.bus_rd_12(rd12),.bus_rd_13(rd13),
.bus_rd_20(rd20),.bus_rd_21(rd21),.bus_rd_22(rd22),.bus_rd_23(rd23),
.bus_rd_30(rd30),.bus_rd_31(rd31),.bus_rd_32(rd32),.bus_rd_33(rd33) .)
H_wr_en_arbiter H_wr_en_arbiter0(.wr_ack(R_wr_ack0),
.clk(clk),
.rst_n(rst_n),
.bus_wr_0(wr00),
.bus_wr_1(wr10),
.bus_wr_2(wr20),
.bus_wr_3(wr30),
.wr_en(wr0));
...... //(此处省略的代码为剩下的3个实例化模块信号,模块编号分别为1、2、3,主要接口分别为.wr_ack(R_wr_ack1),.bus_wr_0(wr01),.bus_wr_1(wr11),.bus_wr_2(wr21),.bus_wr_3(wr31),
.wr_en(wr1);.wr_ack(R_wr_ack2),.bus_wr_0(wr02),.bus_wr_1(wr12),.bus_wr_2(wr22),
.bus_wr_3(wr32),.wr_en(wr2);.wr_ack(R_wr_ack3),.bus_wr_0(wr03),.bus_wr_1(wr13),
.bus_wr_2(wr23),.bus_wr_3(wr33),.wr_en(wr3).)
H_rd_en_arbiter H_rd_en_arbiter0(.rd_ack(R_rd_ack0),
.clk(clk),
.rst_n(rst_n),
.bus_rd_0(rd00),
.bus_rd_1(rd10),
.bus_rd_2(rd20),
.bus_rd_3(rd30),
.rd_en(rd0));
...... //(此处省略的代码为剩下的3个实例化模块信号,模块编号分别为1、2、3,主要接口分别为.rd_ack(R_rd_ack1),.bus_rd_0(rd01),.bus_rd_1(rd11),.bus_rd_2(rd21),.bus_rd_3(rd31),
.rd_en(rd1);.rd_ack(R_rd_ack2),.bus_rd_0(rd02),.bus_rd_1(rd12),.bus_rd_2(rd22),
.bus_rd_3(rd32),.rd_en(rd2);.rd_ack(R_rd_ack3),.bus_rd_0(rd03),.bus_rd_1(rd13),
.bus_rd_2(rd23),.bus_rd_3(rd33),.rd_en(rd3).)
H_mux4to1_wr H_mux4to1_wr0 (.bus_wr_0(HV_wr_0),
.bus_wr_1(HV_wr_1),
.bus_wr_2(HV_wr_2),
.bus_wr_3(HV_wr_3),
.bus_waddr_0(HV_waddr_0),
.bus_waddr_1(HV_waddr_1),
.bus_waddr_2(HV_waddr_2),
.bus_waddr_3(HV_waddr_3),
.bus_wdata_0(HV_wdata_0),
.bus_wdata_1(HV_wdata_1),
.bus_wdata_2(HV_wdata_2),
.bus_wdata_3(HV_wdata_3),
.wr_en(wr0),
.bus_wr(R_wr0),
.bus_waddr(R_waddr0),
.bus_wdata(R_wdata0));
...... //(此处省略的代码为剩下的3个实例化模块信号,模块编号分别为1、2、3,主要接口分别为.bus_wr_0(HV_wr_0),.bus_wr_1(HV_wr_1),.bus_wr_2(HV_wr_2),.bus_wr_3(HV_wr_3),
.bus_waddr_0(HV_waddr_0),.bus_waddr_1(HV_waddr_1),.bus_waddr_2(HV_waddr_2),
.bus_waddr_3(HV_waddr_3),.bus_wdata_0(HV_wdata_0),.bus_wdata_1(HV_wdata_1),
.bus_wdata_2(HV_wdata_2),.bus_wdata_3(HV_wdata_3),.wr_en(wr1、2、3),
.bus_wr(R_wr1、2、3),.bus_waddr(R_waddr1、2、3),.bus_wdata(R_wdata1、2、3).)
H_mux4to1_rd H_mux4to1_rd0(.bus_rd_0(HV_rd_0),
.bus_rd_1(HV_rd_1),
.bus_rd_2(HV_rd_2),
.bus_rd_3(HV_rd_3),
.bus_raddr_0(HV_raddr_0),
.bus_raddr_1(HV_raddr_1),
.bus_raddr_2(HV_raddr_2),
.bus_raddr_3(HV_raddr_3),
.rd_en(rd0),
.bus_rd(R_rd0),
.bus_raddr(R_raddr0));
...... //(此处省略的代码为剩下的3个实例化模块信号,模块编号分别为1、2、3,主要接口分别为.bus_rd_0(HV_rd_0),.bus_rd_1(HV_rd_1),.bus_rd_2(HV_rd_2),.bus_rd_3(HV_rd_3),
.bus_raddr_0(HV_raddr_0),.bus_raddr_1(HV_raddr_1),.bus_raddr_2(HV_raddr_2),
.bus_raddr_3(HV_raddr_3),.rd_en(rd1、2、3),.bus_rd(R_rd1、2、3),
.bus_raddr(R_raddr1、2、3).)
H_mux4to1_rdata H_mux4to1_rdata(.clk(clk),
.rst_n(rst_n),
.bus_rdata_0(R_rdata0),
.rd_en0(rd0),
.bus_rdata0(HV_rdata_0));
...... //(此处省略的代码为该模块剩下的3组信号,接口分别为
.bus_rdata_1(R_rdata1、2、3), .rd_en1(rd1、2、3), .bus_rdata1(HV_rdata_1、2、3).)
H_mux4to1_rw_ack H_mux4to1_rw_ack(.clk(clk),
.rst_n(rst_n),
.wr_en0(wr0),
.rd_en0(rd0),
.v_wr_ack0(R_wr_ack0),
.v_rd_ack0(R_rd_ack0),
.bus_wr_ack0(HV_wr_ack0),
.bus_rd_ack0(HV_rd_ack0));
...... //(此处省略的代码为该模块剩下的3组信号,接口分别为
.wr_en1(wr1、2、3),.rd_en1(rd1、2、3),
.v_wr_ack1(R_wr_ack1、2、3), .v_rd_ack1(R_rd_ack1、2、3),
.bus_wr_ack1(HV_wr_ack1、2、3), .bus_rd_ack1(HV_rd_ack1、2、3).)
endmodule
module H_en_select(bus_wr_0,bus_rd_0,bus_waddr_0,bus_raddr_0,bus_wr_00,bus_wr_01,
bus_wr_02,bus_wr_03, bus_rd_00,bus_rd_01,bus_rd_02, bus_rd_03,
……
bus_wr_3,bus_rd_3,bus_waddr_3,bus_raddr_3, bus_wr_30,bus_wr_31,
bus_wr_32,bus_wr_33, bus_rd_30,bus_rd_31,bus_rd_32,bus_rd_33);
……
parameter addr0 = 2'b00, addr1 = 2'b01, addr2 = 2'b10, addr3 = 2'b11;
assign wcmp_00 = (bus_waddr_0[12:11] == addr0);
assign wcmp_01 = (bus_waddr_0[12:11] == addr1);
assign wcmp_02 = (bus_waddr_0[12:11] == addr2);
assign wcmp_03 = (bus_waddr_0[12:11] == addr3);
assign bus_wr_00 = wcmp_00 & bus_wr_0;
assign bus_wr_01 = wcmp_01 & bus_wr_0;
assign bus_wr_02 = wcmp_02 & bus_wr_0;
assign bus_wr_03 = wcmp_03 & bus_wr_0;
assign wcmp_10 = (bus_waddr_1[12:11] == addr0);
assign wcmp_11 = (bus_waddr_1[12:11] == addr1);
assign wcmp_12 = (bus_waddr_1[12:11] == addr2);
assign wcmp_13 = (bus_waddr_1[12:11] == addr3);
assign bus_wr_10 = wcmp_10 & bus_wr_1;
assign bus_wr_11 = wcmp_11 & bus_wr_1;
assign bus_wr_12 = wcmp_12 & bus_wr_1;
assign bus_wr_13 = wcmp_13 & bus_wr_1;
assign wcmp_20 = (bus_waddr_2[12:11] == addr0);
assign wcmp_21 = (bus_waddr_2[12:11] == addr1);
assign wcmp_22 = (bus_waddr_2[12:11] == addr2);
assign wcmp_23 = (bus_waddr_2[12:11] == addr3);
assign bus_wr_20 = wcmp_20 & bus_wr_2;
assign bus_wr_21 = wcmp_21 & bus_wr_2;
assign bus_wr_22 = wcmp_22 & bus_wr_2;
assign bus_wr_23 = wcmp_23 & bus_wr_2;
assign wcmp_30 = (bus_waddr_3[12:11] == addr0);
assign wcmp_31 = (bus_waddr_3[12:11] == addr1);
assign wcmp_32 = (bus_waddr_3[12:11] == addr2);
assign wcmp_33 = (bus_waddr_3[12:11] == addr3);
assign bus_wr_30 = wcmp_30 & bus_wr_3;
assign bus_wr_31 = wcmp_31 & bus_wr_3;
assign bus_wr_32 = wcmp_32 & bus_wr_3;
assign bus_wr_33 = wcmp_33 & bus_wr_3;
assign rcmp_00 = (bus_raddr_0[12:11] == addr0);
assign rcmp_01 = (bus_raddr_0[12:11] == addr1);
assign rcmp_02 = (bus_raddr_0[12:11] == addr2);
assign rcmp_03 = (bus_raddr_0[12:11] == addr3);
assign bus_rd_00 = rcmp_00 & bus_rd_0;
assign bus_rd_01 = rcmp_01 & bus_rd_0;
assign bus_rd_02 = rcmp_02 & bus_rd_0;
assign bus_rd_03 = rcmp_03 & bus_rd_0;
assign rcmp_10 = (bus_raddr_1[12:11] == addr0);
assign rcmp_11 = (bus_raddr_1[12:11] == addr1);
assign rcmp_12 = (bus_raddr_1[12:11] == addr2);
assign rcmp_13 = (bus_raddr_1[12:11] == addr3);
assign bus_rd_10 = rcmp_10 & bus_rd_1;
assign bus_rd_11 = rcmp_11 & bus_rd_1;
assign bus_rd_12 = rcmp_12 & bus_rd_1;
assign bus_rd_13 = rcmp_13 & bus_rd_1;
assign rcmp_20 = (bus_raddr_2[12:11] == addr0);
assign rcmp_21 = (bus_raddr_2[12:11] == addr1);
assign rcmp_22 = (bus_raddr_2[12:11] == addr2);
assign rcmp_23 = (bus_raddr_2[12:11] == addr3);
assign bus_rd_20 = rcmp_20 & bus_rd_2;
assign bus_rd_21 = rcmp_21 & bus_rd_2;
assign bus_rd_22 = rcmp_22 & bus_rd_2;
assign bus_rd_23 = rcmp_23 & bus_rd_2;
assign rcmp_30 = (bus_raddr_3[12:11] == addr0);
assign rcmp_31 = (bus_raddr_3[12:11] == addr1);
assign rcmp_32 = (bus_raddr_3[12:11] == addr2);
assign rcmp_33 = (bus_raddr_3[12:11] == addr3);
assign bus_rd_30 = rcmp_30 & bus_rd_3;
assign bus_rd_31 = rcmp_31 & bus_rd_3;
assign bus_rd_32 = rcmp_32 & bus_rd_3;
assign bus_rd_33 = rcmp_33 & bus_rd_3;
endmodule
module H_wr_en_arbiter(wr_ack,clk,rst_n,bus_wr_0,bus_wr_1,bus_wr_2,bus_wr_3,wr_en);
……
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n) begin
req1_reg2 <=1'b0; req1_reg3 <=1'b0; req1_reg4 <=1'b0;
req2_reg1 <=1'b1; req2_reg3 <=1'b0; req2_reg4 <=1'b0;
req3_reg1 <=1'b1; req3_reg2 <=1'b1; req3_reg4 <=1'b0;
req4_reg1 <=1'b1; req4_reg2 <=1'b1; req4_reg3 <=1'b1;
end
else if(wr_ack) begin
case (counter)
2'b00: begin
req1_reg2 <=1'b1; req1_reg3 <=1'b1; req1_reg4 <=1'b1;
req2_reg1 <=1'b0; req2_reg3 <=1'b0; req2_reg4 <=1'b0;
req3_reg1 <=1'b0; req3_reg2 <=1'b1; req3_reg4 <=1'b0;
req4_reg1 <=1'b0; req4_reg2 <=1'b1; req4_reg3 <=1'b1;
end
2'b01:begin
req1_reg2 <=1'b0; req1_reg3 <=1'b1; req1_reg4 <=1'b1;
req2_reg1 <=1'b1; req2_reg3 <=1'b1; req2_reg4 <=1'b1;
req3_reg1 <=1'b0; req3_reg2 <=1'b0; req3_reg4 <=1'b0;
req4_reg1 <=1'b0; req4_reg2 <=1'b0; req4_reg3 <=1'b1;
end
2'b10:begin
req1_reg2 <=1'b0; req1_reg3 <=1'b0; req1_reg4 <=1'b1;
req2_reg1 <=1'b1; req2_reg3 <=1'b0; req2_reg4 <=1'b1;
req3_reg1 <=1'b1; req3_reg2 <=1'b1; req3_reg4 <=1'b1;
req4_reg1 <=1'b0; req4_reg2 <=1'b0; req4_reg3 <=1'b0;
end
2'b11:begin
req1_reg2 <=1'b0; req1_reg3 <=1'b0; req1_reg4 <=1'b0;
req2_reg1 <=1'b1; req2_reg3 <=1'b0; req2_reg4 <=1'b0;
req3_reg1 <=1'b1; req3_reg2 <=1'b1; req3_reg4 <=1'b0;
req4_reg1 <=1'b1; req4_reg2 <=1'b1; req4_reg3 <=1'b1;
end
default: begin
req1_reg2 <=1'b0; req1_reg3 <=1'b0; req1_reg4 <=1'b0;
req2_reg1 <=1'b1; req2_reg3 <=1'b0; req2_reg4 <=1'b0;
req3_reg1 <=1'b1; req3_reg2 <=1'b1; req3_reg4 <=1'b0;
req4_reg1 <=1'b1; req4_reg2 <=1'b1; req4_reg3 <=1'b1;
end
endcase
end
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n) counter<=2'b00;
else counter<=counter+2'b01;
end
always @ (*) begin
wr_en[0]=bus_wr_0&(~(req1_reg2&bus_wr_1))&(~(req1_reg3&bus_wr_2))&(~(req1_reg4&bus_wr_3));
wr_en[1]=bus_wr_1&(~(req2_reg1&bus_wr_0))&(~(req2_reg3&bus_wr_2))&(~(req2_reg4&bus_wr_3));
wr_en[2]=bus_wr_2&(~(req3_reg1&bus_wr_0))&(~(req3_reg2&bus_wr_1))&(~(req3_reg4&bus_wr_3));
wr_en[3]=bus_wr_3&(~(req4_reg1&bus_wr_0))&(~(req4_reg2&bus_wr_1))&(~(req4_reg3&bus_wr_2));
end
endmodule
module H_rd_en_arbiter(rd_ack,clk,rst_n,bus_rd_0,bus_rd_1,bus_rd_2,bus_rd_3,rd_en);
……
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)begin
req1_reg2 <=1'b0; req1_reg3 <=1'b0; req1_reg4 <=1'b0;
req2_reg1 <=1'b1; req2_reg3 <=1'b0; req2_reg4 <=1'b0;
req3_reg1 <=1'b1; req3_reg2 <=1'b1; req3_reg4 <=1'b0;
req4_reg1 <=1'b1; req4_reg2 <=1'b1; req4_reg3 <=1'b1;
end
else if(rd_ack)begin
case (counter)
2'b00: begin
req1_reg2 <=1'b1; req1_reg3 <=1'b1; req1_reg4 <=1'b1;
req2_reg1 <=1'b0; req2_reg3 <=1'b0; req2_reg4 <=1'b0;
req3_reg1 <=1'b0; req3_reg2 <=1'b1; req3_reg4 <=1'b0;
req4_reg1 <=1'b0; req4_reg2 <=1'b1; req4_reg3 <=1'b1;
end
2'b01:begin
req1_reg2 <=1'b0; req1_reg3 <=1'b1; req1_reg4 <=1'b1;
req2_reg1 <=1'b1; req2_reg3 <=1'b1; req2_reg4 <=1'b1;
req3_reg1 <=1'b0; req3_reg2 <=1'b0; req3_reg4 <=1'b0;
req4_reg1 <=1'b0; req4_reg2 <=1'b0; req4_reg3 <=1'b1;
end
2'b10:begin
req1_reg2 <=1'b0; req1_reg3 <=1'b0; req1_reg4 <=1'b1;
req2_reg1 <=1'b1; req2_reg3 <=1'b0; req2_reg4 <=1'b1;
req3_reg1 <=1'b1; req3_reg2 <=1'b1; req3_reg4 <=1'b1;
req4_reg1 <=1'b0; req4_reg2 <=1'b0; req4_reg3 <=1'b0;
end
2'b11:begin
req1_reg2 <=1'b0; req1_reg3 <=1'b0; req1_reg4 <=1'b0;
req2_reg1 <=1'b1; req2_reg3 <=1'b0; req2_reg4 <=1'b0;
req3_reg1 <=1'b1; req3_reg2 <=1'b1; req3_reg4 <=1'b0;
req4_reg1 <=1'b1; req4_reg2 <=1'b1; req4_reg3 <=1'b1;
end
default:begin
req1_reg2 <=1'b0; req1_reg3 <=1'b0; req1_reg4 <=1'b0;
req2_reg1 <=1'b1; req2_reg3 <=1'b0; req2_reg4 <=1'b0;
req3_reg1 <=1'b1; req3_reg2 <=1'b1; req3_reg4 <=1'b0;
req4_reg1 <=1'b1; req4_reg2 <=1'b1; req4_reg3 <=1'b1;
end
endcase
end
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n) counter<=2'b00;
else counter<=counter+2'b01;
end
always @(*)begin
rd_en[0]=bus_rd_0&(~(req1_reg2&bus_rd_1))&(~(req1_reg3&bus_rd_2))&(~(req1_reg4&bus_rd_3));
rd_en[1]=bus_rd_1&(~(req2_reg1&bus_rd_0))&(~(req2_reg3&bus_rd_2))&(~(req2_reg4&bus_rd_3));
rd_en[2]=bus_rd_2&(~(req3_reg1&bus_rd_0))&(~(req3_reg2&bus_rd_1))&(~(req3_reg4&bus_rd_3));
rd_en[3]=bus_rd_3&(~(req4_reg1&bus_rd_0))&(~(req4_reg2&bus_rd_1))&(~(req4_reg3&bus_rd_2));
end
endmodule
module H_mux4to1_wr(bus_wr_0, bus_waddr_0, bus_wdata_0,
……
bus_wr_3, bus_waddr_3, bus_wdata_3,wr_en,bus_wr,bus_waddr,bus_wdata);
……
always @(*)begin
case (wr_en)
4'b0001:begin
bus_wdata = bus_wdata_0;
bus_waddr = bus_waddr_0;
bus_wr = bus_wr_0;
end
4'b0010:begin
bus_wdata = bus_wdata_1;
bus_waddr = bus_waddr_1;
bus_wr = bus_wr_1;
end
4'b0100:begin
bus_wdata = bus_wdata_2;
bus_waddr = bus_waddr_2;
bus_wr = bus_wr_2;
end
4'b1000:begin
bus_wdata = bus_wdata_3;
bus_waddr = bus_waddr_3;
bus_wr = bus_wr_3;
end
default: begin
bus_wdata = 32'd0;
bus_waddr = 16'd0;
bus_wr = 1'b0;
end
endcase
end
endmodule
moduleH_mux4to1_rd(bus_rd_0,bus_rd_1,bus_rd_2,bus_rd_3,bus_raddr_0,bus_raddr_1,
bus_raddr_2,bus_raddr_3, rd_en,bus_rd,bus_raddr);
……
always @(*)begin
case (rd_en)
4'b0001:begin
bus_raddr = bus_raddr_0;
bus_rd = bus_rd_0;
end
4'b0010:begin
bus_raddr = bus_raddr_1;
bus_rd = bus_rd_1;
end
4'b0100:begin
bus_raddr = bus_raddr_2;
bus_rd = bus_rd_2;
end
4'b1000:begin
bus_raddr = bus_raddr_3;
bus_rd = bus_rd_3;
end
default: begin
bus_raddr = 16'd0;
bus_rd = 1'b0;
end
endcase
end
endmodule
moduleH_mux4to1_rdata(clk,rst_n,bus_rdata_0,bus_rdata_1,bus_rdata_2,
bus_rdata_3, rd_en0,rd_en1,rd_en2, rd_en3, bus_rdata0,bus_rdata1,bus_rdata2,bus_rdata3);
……
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
rd0_0 <= 4'd0;
rd1_1 <= 4'd0;
rd2_2 <= 4'd0;
rd3_3 <= 4'd0;
end
else begin
rd0_0 <= rd_en0;
rd1_1 <= rd_en1;
rd2_2 <= rd_en2;
rd3_3 <= rd_en3;
end
end
always @(*)begin
if (rd0_0==4'b0001)bus_rdata0 = bus_rdata_0;
else if(rd1_1==4'b0001)bus_rdata0 = bus_rdata_1;
else if(rd2_2==4'b0001)bus_rdata0 = bus_rdata_2;
else if(rd3_3==4'b0001)bus_rdata0 = bus_rdata_3;
else bus_rdata0 = 16'd0;
end
always @(*)begin
if (rd0_0==4'b0010)bus_rdata1 = bus_rdata_0;
else if(rd1_1==4'b0010)bus_rdata1 = bus_rdata_1;
else if(rd2_2==4'b0010)bus_rdata1 = bus_rdata_2;
else if(rd3_3==4'b0010)bus_rdata1 = bus_rdata_3;
else bus_rdata1 = 16'd0;
end
always @(*)begin
if (rd0_0==4'b0100)bus_rdata2 = bus_rdata_0;
else if(rd1_1==4'b0100)bus_rdata2 = bus_rdata_1;
else if(rd2_2==4'b0100)bus_rdata2 = bus_rdata_2;
else if(rd3_3==4'b0100)bus_rdata2 = bus_rdata_3;
else bus_rdata2 = 16'd0;
end
always @(*)begin
if (rd0_0==4'b1000)bus_rdata3 = bus_rdata_0;
else if(rd1_1==4'b1000)bus_rdata3 = bus_rdata_1;
else if(rd2_2==4'b1000)bus_rdata3 = bus_rdata_2;
else if(rd3_3==4'b1000)bus_rdata3 = bus_rdata_3;
else bus_rdata3 = 16'd0;
end
endmodule
module H_mux4to1_rw_ack(clk,rst_n,wr_en0, rd_en0, v_wr_ack0, v_rd_ack0, bus_wr_ack0, bus_rd_ack0,
……
wr_en3, rd_en3,v_wr_ack3, v_rd_ack3, bus_wr_ack3,bus_rd_ack3);
……
assign bus_wr_ack0=(wr_en0[0]&v_wr_ack0)|(wr_en1[0]&v_wr_ack1)|( wr_en2[0]&v_wr_ack2)|(wr_en3[0]&v_wr_ack3);
assign bus_wr_ack1=(wr_en0[1]&v_wr_ack0)|(wr_en1[1]&v_wr_ack1)|( wr_en2[1]&v_wr_ack2)|(wr_en3[1]&v_wr_ack3);
assign bus_wr_ack2=(wr_en0[2]&v_wr_ack0)|(wr_en1[2]&v_wr_ack1)|( wr_en2[2]&v_wr_ack2)|(wr_en3[2]&v_wr_ack3);
assign bus_wr_ack3=(wr_en0[3]&v_wr_ack0)|(wr_en1[3]&v_wr_ack1)|( wr_en2[3]&v_wr_ack2)|(wr_en3[3]&v_wr_ack3);
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
rd0_0 <= 4'd0;
rd1_1 <= 4'd0;
rd2_2 <= 4'd0;
rd3_3 <= 4'd0;
end
else begin
rd0_0 <= rd_en0;
rd1_1 <= rd_en1;
rd2_2 <= rd_en2;
rd3_3 <= rd_en3;
end
end
assign bus_rd_ack0=(rd0_0[0]&v_rd_ack0)|(rd1_1[0]&v_rd_ack1)|(rd2_2[0]&v_rd_ack2)|(rd3_3[0]&
v_rd_ack3);
assign bus_rd_ack1=(rd0_0[1]&v_rd_ack0)|(rd1_1[1]&v_rd_ack1)|(rd2_2[1]&v_rd_ack2)|(rd3_3[1]&
v_rd_ack3);
assign bus_rd_ack2=(rd0_0[2]&v_rd_ack0)|(rd1_1[2]&v_rd_ack1)|(rd2_2[2]&v_rd_ack2)|(rd3_3[2]&
v_rd_ack3);
assign bus_rd_ack3=(rd0_0[3]&v_rd_ack0)|(rd1_1[3]&v_rd_ack1)|(rd2_2[3]&v_rd_ack2)|(rd3_3[3]&
v_rd_ack3);
endmodule
本设计已经在“三维视频处理系统芯片动态可重构可编程体系结构研究”项目中加以采用,经过了FPGA开发的实际测试,测试结果表明该设计电路的功能完全正确,可以可靠工作,各项功能及性能指标均符合要求,实现了发明的目的。
机译: 处理器阵列访问与输出处理器耦合的存储器阵列中的数据,并具有到输入定序器的反馈路径,用于以不同的模式存储数据
机译: 用于改善存储器系统内的页面访问和块传输的电路,系统和方法(用于改善存储器系统中的页面访问和块传输的电路,系统和方法)
机译: 处理器访问以存储在电话交换机中的电路-通过停止发送程序命令的时钟脉冲来控制信令