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Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

机译：通过同步多线程将线程级并行性转换为指令级并行性

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Jack L. Lo; Susan J. Eggers; Joel S. Emer; Henry M. Levy; Rebecca L. Stamm; Dean M. Tullsen;
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年度 1997
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1. Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor [J] . Fredrik Warg, Per Stenstrom International journal of parallel programming . 2008,第2期

机译：双线程推测：一种在同步多线程处理器上发现线程级并行性的简单方法
2. Exploiting thread-level and instruction-level parallelism to cluster mass spectrometry data using multicore architectures [J] . Fahad Saeed, Jason D. Hoffert, Trairak Pisitkun, Network Modeling Analysis in Health Informatics and Bioinformatics . 2014,第1期

机译：使用多核体系结构利用线程级和指令级并行性对质谱数据进行聚类
3. A VLIW processor using both thread-level and instruction-level parallelism [J] . Hiroyuki Shimajiri, Takeo Yoshida 電子情報通信学会技術研究報告. コンピュ-タシステム. Computer Systems . 2000,第86期

机译：使用线程级和指令级并行性的VLIW处理器
4. Runtime support for integrating precomputation and thread-level parallelism on simultaneous multithreaded processors [C] . Tanping Wang, Filip Blagojevic, Dimitrios S. Nikolopoulos Proceedings of the 7th workshop on Workshop on languages, compilers, and run-time support for scalable systems . 2004

机译：运行时支持，用于在同时多线程处理器上集成预计算和线程级并行性
5. High Performance Soft Processor Architectures for Applications with Irregular Data- and Instruction-Level Parallelism [D] . Aasaraai, Kaveh 2014

机译：具有不规则数据和指令级并行性的应用的高性能软处理器架构
6. Exploiting Thread-Level and Instruction-Level Parallelism to Cluster Mass Spectrometry Data using Multicore Architectures [O] . Fahad Saeed, Jason D. Hoffert, Trairak Pisitkun, -1

机译：利用多核体系结构利用线程级和指令级并行性对质谱数据进行聚类
7. Runtime Support for Integrating Precomputation and Thread-Level Parallelism on Simultaneous Multithreaded Processors [O] . Wang, T., Blagojevic, F., Nikolopoulos, Dimitrios 2004

机译：在同时多线程处理器上集成预计算和线程级并行性的运行时支持
8. In Search of Speculative Thread-Level Parallelism [R] . Oplinger, J. T. , Heine, D. L. , Lam, M. S. 1999

机译：寻找思辨线程级并行

Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

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