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Formation of Aminosilane and Thiol Monolayers on Semiconductor Surfaces and Bulk Wet Etching of III--V Semiconductors

机译:半导体表面上氨基硅烷和硫醇单分子膜的形成以及III-V半导体的本体湿法蚀刻

摘要

Continuous scaling down of the dimensions of electronic devices has made present day computers more powerful. In the front end of line, the minimum lateral dimensions in a transistor have shrunk from 45 nm in 2007 to 22 nm currently, and the gate oxide film thickness is two to three monolayers. This reduction in dimensions makes surface preparation an increasingly important part of the device fabrication process. The atoms or molecules that terminate surfaces function as passivation layers, diffusion barriers, and nucleation layers. In the back end of line, metal layers are deposited to connect transistors. We demonstrate a reproducible process that deposits a monolayer of aminopropyltrimethoxysilane molecules less than one nanometer thick on a silicon dioxide surface. The monolayer contains a high density of amine groups that can be used to deposit Pd and Ni and subsequently Co and Cu to serve as the nucleation layer in an electroless metal deposition process. Because of the shrinking device dimensions, there is a need to find new transistor channel materials that have high electron mobilities along with narrow band gaps to reduce power consumption. Compound III--V channel materials are candidates to enable increased performance and reduced power consumption at the current scaled geometries. But many challenges remain for such high mobility materials to be realized in high volume manufacturing. For instance, low defect density (1E7 /cm²) III--V and Ge on Si is the most fundamental issue to overcome before high mobility materials become practical. Unlike Si, dry etching of III-V semiconductor surfaces is believed to be difficult and uncontrollable. Therefore, new wet etching chemistries are needed. Si has been known to passivate by etching in hydrofluoric acid, but similar treatments on III--Vs are known to temporarily hydrogen passivate the surfaces. However, any subsequent exposure to the ambient reoxidizes the surface, resulting in a chemically unstable and high defect density interface. This work compares old and new wet etching chemistries and investigates new methods of passivating the III--V semiconductors.
机译:电子设备尺寸的不断缩小使当今的计算机变得更加强大。在生产线的前端,晶体管的最小横向尺寸从2007年的45 nm缩小到目前的22 nm,栅氧化膜厚度为2到3个单层。尺寸的减小使表面准备成为器件制造过程中越来越重要的部分。终止表面的原子或分子充当钝化层,扩散势垒和成核层。在生产线的后端,沉积金属层以连接晶体管。我们展示了一种可重现的过程,该过程在二氧化硅表面上沉积了一层小于一层纳米的氨丙基三甲氧基硅烷分子。单层包含高密度的胺基,可用于沉积Pd和Ni,随后沉积Co和Cu,以在化学镀金属沉积过程中用作成核层。由于器件尺寸的缩小,需要寻找具有高电子迁移率和窄带隙的新型晶体管沟道材料,以降低功耗。化合物III-V通道材料是候选材料,可以在当前缩放的几何尺寸下提高性能并降低功耗。但是,要在大批量生产中实现这种高迁移率的材料仍然面临许多挑战。例如,在高迁移率材料成为现实之前,要克服的最基本问题是低缺陷密度(1E7 /cm²)III-V和Si上的Ge。与Si不同,III-V族半导体表面的干法蚀刻被认为是困难且不可控的。因此,需要新的湿法蚀刻化学。已知通过在氢氟酸中蚀刻可钝化Si,但是已知对III-Vs进行类似处理可暂时使表面氢钝化。然而,任何随后暴露于环境中都会使表面再氧化,从而导致化学上不稳定且缺陷密度高的界面。这项工作比较了旧的和新的湿法蚀刻化学,并研究了钝化III-V半导体的新方法。

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    Jain Rahul;

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  • 年度 2012
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