LDMOS devices with grounded gate shield structures variations were simulated and tested, aiming to address hot carrier immunity and robustness concurrently. Optimal configuration of grounded gate shield structure was found to reduce local electrical field strength at gate-to-drain overlap for better hot carrier immunity, and to achieve uniform E-field distribution on drain side for robustness as well. Design trade off of hot carrier immunity (HCI) and robustness is analyzed by simulation and silicon data.
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