This summary report presents in brief form the results obtained during a study of small-scale, fault-tolerant (highly reliable) digital hardware, performed under ESTEC contract 2253/74 AK. The report contains an introductory section outlining the raison d’être of the study, its scope, and its objectives. The principal fault-tolerant techniques studied are then described briefly, together with the conclusions about their value and applicability. The results of a design exercise on a simple microprogrammed controller are described and compared with those of a conventional fault-tolerant design using triple modular redundancy (TMR). The results of supporting studies on limitations and implications of technology particularly large scale integrated circuits (LSI) and of reliability assessment and fault diagnosis are also presented.
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