Performance of the Butterfly Processor-Memory Interconnection in a Vector Environment

摘要

A fundamental hurdle impeding the development of large N common memory multiprocessors is the performance limitation in the switch connecting the processors to the memory modules. Multistage networks currently considered for this connection have a memory latency which grows like alpha log sub 2 N*. For scientific computing, it is natural to look for a multiprocessor architecture that will enable the use of vector operations to mask memory latency. The problem to be overcome here is the chaotic behavior introduced by conflicts occurring in the switch. In this paper we examine the performance of the butterfly or indirect binary n-cube network in a vector processing environment. We describe a simple modification of the standard 2X2 switch node used in such networks which adaptively removes chaotic behavior during a vector operation. (ERA citation 10:022255)