Quaternary Decision Diagram Machine and the Optimization of Its Code.

摘要

We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28- 2.02 times when QDDs are chosen. We consider 1-and 2- address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.