Design of the Processor for Software Compatible Avionic Computer Family.

摘要

This report presents the design of a microprogrammable processor which emulates the baseline instruction set of the Software-Compatible Avionic Computer Family. The general architecture of this processor includes 16/32 bit word lengths, hardware fixed point arithmetic, firmware floating point arithmetic, and hardware vectored interrupts. The processors uses a flexible internal bus (I-BUS) to interface with memory modules, programmed input/output channels, and DMA channels. Integrated circuit devices from the AM 2900 family are used to realize the design. The processor's arithmetic and logic unit contains four AM 2901A bit slice devices which are cascaded by an AM 2902 carry look-ahead generator. The processor's control unit uses an AM 2910 microsequencer to address control memory in a first level pipeline mode. The processor's hardware vectored interrupt system is managed by two AM 2914 priority interrupt encoders. Evaluation of the processor design determined that the processor's operational speed falls below the design goal of 200 to 500 KOPS. The report concludes with recommendations for improving the processor's speed by adding hardware to facilitate floating point arithmetic and to pipeline I/O transfers over the I-BUS. (Author)