Bus Interface Unit Design for the Distributed Processor/Memory System.

摘要

This report describes the design of the Bus Interface Unit for the Distributed Processor/Memory (DP/M) System. The DP/M System, which is being developed by the Air Force Avionics Laboratory, is a concept to integrate avionics on board an aircraft by utilizing a number of programmable processor/memory elements (PE's) in a distributed (decentralized) network. All the PE's in the system are interconnected by a pair of redundant global buses and PE's in an affinity group are additionally interconnected by a local bus. This effort involves the design of the Bus Interface Unit (BIU) of the PE. The BIU interfaces the parallel-data PE processor with the two redundant serial global buses and the serial local bus. The BIU has been designed as an interrupt driven microprogrammed processor. The design uses a bipolar bit-slice microprocessor, specifically the Am2900 Bipolar Microprocessor Family, for emulating the BIU functions. This report starts with a brief description of the DP/M System, followed by a detailed description of the BIU functions. Then the hard-ware, the microword format, and the microroutines are described. A discussion on the design effort is presented at the end, and recommendations are made for system improvement. (Author)