多处理器系统中基于FPGA的VME总线接口设计

摘要

Based on analysis of the timing of VME bus, a VME slave interface was designed by introducing FPGA. Utilizing the characters of low-development cost, low power consumption and high density of FPGA and the idea of compact design, the double port RAM and timing control module were integrated in one chip of FPGA to realize the communication function of VME interface. The whole design is flexible and costless. The results of system simulation and prototype test show that the VME interface works reliably and easily.%在分析VME时序的基础上介绍了一种采用FPGA进行VME总线接口设计的方法.该方法利用FPGA低开发成本、低功耗、高集成度的特点,采用紧凑设计思想,通过把双端口RAM和时序控制模块结合在一起完整实现VME接口通信功能,并实现在一个FPGA芯片中,使整个设计的灵活性增强、开发成本降低.系统仿真和样机试验结果表明:该接口数据发送和接收时序正确,逻辑严密,运行可靠.