The Programmable Matched Filter: A Design Study.

摘要

The Programmable Matched Filter was envisioned as a flexible approach toward real-time, multi-dimensional matched filtering problems. Its design features multiple, parallel arithmetic elements communicating with multiple memories via a crossbar switch at a clock rate of 16.7 MHz. The machine will sustain a throughput rate of more than 500 million real operations per second, or more than six Cray-1 computers. The extensive use of low-dissipation CMOS technology in large scale integrated circuits yields an estimated total of 5200 integrated circuits, dissipating less than one kilowatt, occupying 0.2 cubic meters and weighing approximately fifty kilograms. (Author)