A New Distributed Arithmetic Algorithm and Its Hardware Architecture for the Discrete Hartley Transform

摘要

This paper presents a new distributed arithmetic (DA) algorithm and its associated hardware architecture for the one-dimensional (1D) discrete Hartley transform (DHT) of any length. Using the similar idea to the Chirp-Z transform, the author derives a new algorithm that can formulate the 1D DHT of any length into cyclic convolution. By exploiting the good feature of the cyclic convolution, we can realize the 1D DHT of any length in an array architecture based on the popular DA-based approach, utilize identical ROM modules, and eliminate the accumulation loop in the processing elements (PEs). The use of identical ROM modules can simplify the ROM design process. The elimination of the accumulation loop of the PEs in conventional DA-based architecture can further increase the processing speed by applying the pipeline technique. Moreover, the presented design possesses the good features of the DA-based architectures, including low hardware cost, high computing speed, low input/output (I/O) cost, and high flexibility in transform length.