Design and operation of a series array of voltage doubler cells for rapid-single-flux-quantum digital-to-analog converters

摘要

The output voltage of a rapid-single-flux-quantum digital-to-analog converter (RSFQ-DAC) is generated with a voltage multiplier (VM) that comprises multiple voltage mirror cells. We have demonstrated a new operation mode of a voltage mirror cell. It is a second-mode operation that doubles the input voltage, like the second-order Shapiro step. That is, a single cell works as a voltage doubler (VD). In this work, we propose a new parameter set of the VD (VD revision 1: VDrl) that improves the tolerance for multi-stage operation. Experimental results of a 16-stage VDrl circuit are presented.