The integration of EMC constraints in the design of high-density logic integrated circuits

摘要

A method of reducing the level of interference transmitted as voltage variations on the input, output and supply connections to integrated circuits (ICs) has been developed. The method is applicable to all types of digital ICs including high-density circuit substrates. The method analyses the analogue behaviour of the IC and simulates the interference source as two current generators, one on the VDD supply (ivdd) and one on the VSS ground connection (ivss). The method therefore takes account of the entire supply circuit including the IC package, the decoupling network and the supply connections themselves. The simulation calculates the resulting noise level on the input, output and supply connections to the IC.