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Flip-chip fabrication of nanoscale co-planar embedded electrodes with controlled exposed areas

机译:具有受控暴露区域的纳米级共面嵌入式电极的倒装芯片制造

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摘要

We discuss the fabrication of closely spaced nanoscale embedded co-planar electrodes with concealed contact wires, using a GaAs-based flip-chip technology. The co-planarity of the electrodes with the substrate and the low roughness of the exposed surface are achieved by templating the deposition of both the dielectric and electrode metal onto a smooth GaAs substrate. The resulting electrodes, with sizes of around 300 nm and separations as low as 25 nm, have RMS roughnesses of less than 0.2 nm and a co-planarity of around 1 nm.
机译:我们讨论了使用基于GaAs的倒装芯片技术制造具有隐藏式接触线的紧密间隔的纳米级嵌入式共面电极。电极与基板的共面性和暴露表面的低粗糙度是通过将电介质和电极金属都沉积在光滑的GaAs基板上来实现的。所得电极的尺寸约为300 nm,间距低至25 nm,RMS粗糙度小于0.2 nm,共面约为1 nm。

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