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Nanoslits in silicon chips

机译:硅芯片中的纳米缝

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Potassium hydroxide (KOH) etching of a patterned < 100 > oriented silicon wafer produces V-shaped etch pits. We demonstrate that the remaining thickness of silicon at the tip of the etch pit can be reduced to similar to 5 mu m using an appropriately sized etch mask and optical feedback. Starting from such an etched chip, we have developed two different routes for fabricating 100 nm scale slits that penetrate through the macroscopic silicon chip (the slits are similar to 850 mu m wide at one face of the chip and gradually narrow to similar to 100-200 nm wide at the opposite face of the chip). In the first process, the etched chips are sonicated to break the thin silicon at the tip of the etch pit and then further KOH etched to form a narrow slit. In the second process, focused ion beam milling is used to etch through the thin silicon at the tip of the etch pit. The first method has the advantage that it uses only low-resolution technology while the second method offers more control over the length and width of the slit. Our slits can be used for preparing mechanically stable, transmission electron microscopy samples compatible with electrical transport measurements or as nanostencils for depositing nanowires seamlessly connected to their contact pads.
机译:图案化的<100>取向硅片的氢氧化钾(KOH)蚀刻产生V形蚀刻坑。我们证明,使用适当大小的蚀刻掩模和光学反馈,可以将蚀刻凹坑尖端的硅剩余厚度减小到大约5微米。从这种蚀刻的芯片开始,我们已经开发出两种不同的方法来制造可穿透宏观硅芯片的100 nm尺寸的狭缝(狭缝在芯片的一个面上类似于850μm的宽度,并逐渐变窄为类似于100-nm芯片另一面的宽度为200 nm)。在第一个过程中,对经过蚀刻的芯片进行超声处理,以使其在蚀刻坑的尖端断裂,然后进一步KOH蚀刻以形成狭窄的缝隙。在第二个过程中,使用聚焦离子束铣削以蚀刻穿过蚀刻坑尖端的薄硅。第一种方法的优点是仅使用低分辨率技术,而第二种方法则可以更好地控制狭缝的长度和宽度。我们的狭缝可用于制备与电迁移测量兼容的机械稳定的透射电子显微镜样品,或者用作纳米模板,用于沉积无缝连接到其接触垫的纳米线。

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