A LOW PHASE NOISE DESIGN FOR ULTRAWIDEBAND FREQUENCY SYNTHESIZER

摘要

A low phase-noise frequency synthesizer design for ultrawideband is demonstrated in a 0.18-μm CMOS process. It combines a low phase-noise voltage-controlled oscillator with two-stage dividers and a switched buffer multiplexer with low layout complexity. Because of the symmetrical independent architecture of this switch buffer design, it can reduce the additional phase noise created by the traditional multiplexer stage. Here, this low phase noise design in three LO bands (8448, 4224, and 2112 MHz) is demonstrated. The measurement shows that in these three LO band, this new structure can achieve phase noise of less than -121 dBc/Hz at 1 MHz offset. The frequency tuning range is 10% while consuming only 52.2 mW from a 1.8-V supply.