DESIGN OF RESISTIVE DOUBLE-BALANCED MIXER IN 0.18-μm CMOS TECHNOLOGY WITH LOW-POWER BULK-INJECTION TECHNIQUE FOR 5.8-GHz DSRC APPLICATIONS

摘要

This article shows a 0.18-μm CMOS resistive double-balanced mixer design with low-noise figure and high-linearity performances consuming only 0.21-mW dc power, for 5.8-GHz dedicated short-range communications (DSRC) applications. The local oscillator (LO) signal is applied to the bulk and the source terminals differentially to reduce the required LO power without needs of impedance matching. The on-chip central-taped transformers are utilized as balance-to-unbalance function for RF and LO ports, and the differential output is used as well for intermediate-frequency (IF) port. The measured data exhibit -8-dB conversion gain and 8-dB noise figure at 5.8 GHz of RF frequency and 100 MHz of IF frequency, while the input 1-dB compression point and the input interception point in the third order (IP3) are about -7.5 and 3 dBm, respectively, to fulfill the DSRC requirements.