Asymmetrical Increase of Memory Window in MFIS Devices After Avalanche Hole Injection

摘要

We have investigated the effects of charge trapping on the asymmetrical increase of the memory window in metal-ferroelectric-insulator-semiconductor (MFIS) devices. We suggest that defect centers located at the ferroelectric-insulator interface play important roles for generating the asymmetrical increase of the memory window. For example, hole trapping atear the SBN-Y_2O_3 SiO_2 interface via avalanche hole injection from the Si substrate results in the preferential domain switching, causing the asymmetrical increase of the memory window.